View VS6624_4774486.PDF datasheet online --- IC-ON-LINE

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preliminary data this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. july 2007 rev 7 1/106 1 vl6624 VS6624 1.3 megapixel single-chip camera module features 1280h x 1024v active pixels 3.0 m pixel size, 1/3 inch optical format rgb bayer color filter array integrated 10-bit adc integrated digital image processing functions, including defect correction, lens shading correction, image scaling, demosaicing, sharpening, gamma correction and color space conversion embedded camera controller for automatic exposure control, automatic white balance control, black level compensation, 50/60 hz flicker cancelling and flashgun support fully programmable frame rate and output derating functions up to 15 fps sxga progressive scan low power 30 fps vga progressive scan itu-r bt.656-4 yuv (ycbcr) 4:2:2 with embedded syncs, yuv (ycbcr) 4:0:0, rgb 565, rgb 444, bayer 10-bit or bayer 8-bit output formats 8-bit parallel video interface, horizontal and vertical syncs, 54mhz (max) clock two-wire serial control interface on-chip pll, 6.5 to 54 mhz clock input analog power supply, from 2.4 to 3.0 v separate i/o power supply, 1.8 or 2.8 v levels integrated power management with power switch, automatic power-on reset and power- safe pins low power consumption, ultra low standby current triple-element plastic lens, f# 3.2, 52 horizontal field of view (VS6624) 8.0 x 8.0 x 6.1mm fixed focus camera module with embedded passives (VS6624) 20-wire fpc attachment with board-to-board connector, 22 mm total length, for mobile application only 24-pin (itu) shielded socket options applications mobile phone videophone medical machine vision toys pda biometry bar code reader lighting control description the vl6624/VS6624 is an sxga cmos color digital camera featuring low size and low power consumption targeting mobile applications. this complete camera module is ready to connect to camera enabled baseband processors, back-end ic devices or pda engines. www.st.com
contents vl6624/VS6624 2/106 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 electrical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 video pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 microprocessor functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 streaming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 input clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 frame control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 sensor mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 image size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 cropping module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 zoom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 frame rate control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 horizontal mirror and vertical flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 video pipe setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 viewlive operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 output data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 line / frame blanking data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 yuv 4:2:2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 yuv 4:0:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 rgb and bayer 10 bit data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
vl6624/VS6624 contents 3/106 manipulation of rgb data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 bayer 8-bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 data synchronization methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 embedded codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 prevention of false synchronization codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 mode 1 (itu656 compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mode 2 logical dma channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 vsync and hsync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 horizontal synchronization signal (hsync) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 vertical synchronization (vsync) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 pixel clock (pclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 master / slave operation of plck. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 initial power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 minimum startup command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 host communication - i2c control interface . . . . . . . . . . . . . . . . . . . . . 35 10.1 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2 detailed overview of the message format . . . . . . . . . . . . . . . . . . . . . . . . 36 10.3 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.4 start (s) and stop (p) conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.6 index space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.7 types of messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.8 random location, single data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.9 current location, single data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.10 random location, single data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.11 multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.12 multiple location read stating from the current location . . . . . . . . . . . . . . 43 10.13 multiple location read starting from a random location . . . . . . . . . . . . . . . 44
contents vl6624/VS6624 4/106 11 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 low level control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 user interface map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12 optical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.1 average sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.2 spectral response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13.4 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13.5 chip enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13.6 i2c slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.7 parallel data interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14 user precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 15 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 15.1 smop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 15.2 lga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 16 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
vl6624/VS6624 list of tables 5/106 list of tables table 1. VS6624 signal description of 20-pin flex connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. itu656 embedded synchronization code definition (even frames). . . . . . . . . . . . . . . . . . . 27 table 4. itu656 embedded synchronization code definition (odd frames). . . . . . . . . . . . . . . . . . . . 27 table 5. mode 2 - embedded synchronization code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 7. low-level control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 8. device parameters [read only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 9. host interface manager control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 10. host interface manager status [read only]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 11. run mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 12. mode setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 13. pipe setup bank0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 14. pipe setup bank1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 15. viewlive control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 16. viewlive status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 17. power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 18. video timing parameter host inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 19. video timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 20. frame dimension parameter host inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 21. static frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 22. automatic frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 23. exposure controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 24. white balance control parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 25. sensor setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 26. image stability [read only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 27. flash control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 28. flash status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 29. scythe filter controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 30. jack filter controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 31. demosaic control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 32. colour matrix dampers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 33. peaking control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 34. pipe0 rgb to yuv matrix manual control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 35. pipe1 rgb to yuv matrix manual control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 36. pipe 0 gamma manual control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 37. pipe 1 gamma manual control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 38. fade to black . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 39. output formatter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 40. nora controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 41. optical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 42. VS6624 average sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 43. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 44. supply specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 45. dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 46. typical current consumption - sensor mode vga 30 fps . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 47. typical current consumption - sensor mode sxga 15 fps. . . . . . . . . . . . . . . . . . . . . . . . . 90 table 48. external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 49. serial interface voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
list of tables vl6624/VS6624 6/106 table 51. parallel data interface timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 52. lga package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 01 table 53. vl6524 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 54. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 55. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
vl6624/VS6624 list of figures 7/106 list of figures figure 1. vl6624/VS6624 simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. state machine at power -up and user mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. crop controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. viewlive frame output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6. standard y cb cr data order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. y cb cr data swapping options register 0x2294 byuvsetup . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. yuv 4:0:0 format encapsulated in itu stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. rgb and bayer data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10. bayer 8 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11. itu656 frame structure with even codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. mode 2 frame structure (vga example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. mode 2 frame structure (vga example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. hsync timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15. vsync timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16. qclk options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17. qualification clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 18. write message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 19. read message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 20. detailed overview of message format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 21. device addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 22. sda data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 23. start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 24. data acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 25. internal register index space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 26. random location, single write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 27. current location, single read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 28. 16-bit index, 8-bit data random index, single data read . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 29. 16-bit index, 8-bit data multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 30. multiple location read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 31. multiple location read starting from a random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 32. quantum efficiency (h8s1 - 3.0 m pixel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 33. voltage level specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 34. timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 35. sda/scl rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 36. parallel data output video timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 37. package outline socket module VS6624q0kp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 38. package outline socket module VS6624q0kp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 39. package outline fpc module VS6624p0lp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 40. package outline fpc module VS6624p0lp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 41. vl6524qomh outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 03
overview vl6624/VS6624 8/106 1 overview the vl6624/VS6624 is a sxga resolution cmos imaging device designed for low power systems. manufactured using st 0.18 m cmos imaging process, it integrates a high-sensitivity pixel array, a digital image processor and camera control functions. the VS6624 is capable of streaming sxga video up to 15 fps, with itu-r bt.656-4 yuv 4:2:2 frame format. it supports both 1.8 v and 2.8 v interface and requires a 2.4 to 3.0 v analog power supply. typically, the VS6624 can operate as a 2.8 v single supply camera or as a 1.8 v interface / 2.8 v supply camera. the integrated pll allows for low frequency system clock, and flexibility for successful emc integration. the VS6624 camera module uses st?s 2 nd generation ?smop2? packaging technology: the sensor, lens and passives are assembled, tested and focused in a fully automated process, allowing high volume and low cost production. the device contains an embedded video processor and delivers fully color processed images at up to 15 frames per second sxga and up to 30 fps vga. the video data is output over an 8-bit parallel bus in rgb, ycbcr or bayer formats. the vl6624/VS6624 requires an analogue power supply of between 2.4 v to 3.0 v and a digital supply of either 1.8 v or 2.8 v (dependant on interface levels required). an input clock is required in the range 6.5 mhz to 54 mhz. the vl6624/VS6624 is controlled via an i2c interface. it also includes a wide range of image enhancement functions, designed to ensure high image quality, these include: automatic exposure control automatic white balance lens shading compensation defect correction algorithms demosaic (bayer to rgb conversion) colour space conversion sharpening gamma correction flicker cancellation nora noise reduction algorithm intelligent image scaling
vl6624/VS6624 electrical interface 9/106 2 electrical interface the vl6624/VS6624 fpc board to board connector has 20 electrical connections which are listed in ta b l e 1 . the package details of the flex connector are shown in figure 39 and figure 40 . table 1. VS6624 signal description of 20-pin flex connector the package details and electrical connections of the 24pin socket device are shown in figure 37 and figure 38 . table 2: pad pad name i/o description 1 gnd pwr analogue ground 2 hsync out horizontal synchronization output 3 vsync out vertical synchronization output 4 scl in i2c clock input 5 clk in clock input - 6.5mhz to 54mhz 6 sda i/o i2c data line 7 vdd pwr digital supply 1.8 v or 2.8 v 8 avdd pwr analogue supply 2.4 v to 3.0 v 9 pclk out pixel qualification clock 10 ce in chip enable signal active high 11 d5 out data output d5 12 d4 out data output d4 13 gnd pwr digital ground 14 d3 out data output d3 15 d2 out data output d2 16 d1 out data output d1 17 d0 out data output d0 18 d6 out data output d6 19 d7 out data output d7 20 fso out flash output
system architecture vl6624/VS6624 10/106 3 system architecture the VS6624 consists of the following main blocks: sxga-sized pixel array video timing generator video pipe statistics gathering unit clock generator microprocessor a simplified block diagram is shown figure 1 . figure 1. vl6624/VS6624 simplified block diagram 3.1 operation a video timing generator controls a sxga-sized pixel array to produce raw bayer images. the analogue pixel information is digitized and passed into the video pipe. the video pipe contains a number of different functions (explained in detail later). at the end of the video pipe data is output to the host system over an 8-bit parallel interface along with qualification signals. the whole system is controlled by an embedded microprocessor that is running firmware stored in an internal rom. the external host communicates with this microprocessor over an i2c interface. the microprocessor does not handle the video data itself but is able to control all the functions within the video pipe. real-time information about the video data is gathered by a statistics engine and is available to the microprocessor. the processor uses microprocessor sda scl ce avdd hsync pclk d[0:7] clk vsync clock generator i2c statistics gathering video timing generator reset vreg vdd i2c interface fso gnd gnd sxga pixel array video pipe
vl6624/VS6624 system architecture 11/106 this information to perform real-time image control tasks such as automatic exposure control. 3.2 video pipe the main functions contained within the vl6624/VS6624 video processing pipe are as follows. gain and offset this function is used to apply gain and offset to data coming from the sensor array. the microprocessor applies gain and offset values are controlled by the automatic exposure and white balance algorithms. anti-vignette this function is used to compensate for the radial roll-off in intensity caused by the lens. by default the anti-vignette setting matches the lens used in this module and does not need to be adjusted. crop this function allows the user to select an arbitrary window of interest (woi) from the sxga-sized pixel array, note that the crop size should not be smaller that the output size. it is fully accessible to the user. scaler the scaler module performs real time downscaling, in both the horizontal and vertical domain, of the bayer image data this is achieved by sample-rate conversion. the scaler is capable of downscaling from 1.0x to 10x the input number of pixels and lines, in steps of 1/16. derating the VS6624 contains an internal derating module. this is designed to reduce the peak output data rate of the device by spreading the data over the whole frame period and allowing a subsequent reduction in output clock frequency. the maximum achievable derating factor is x100 for an equivalent scale factor of x10 downscale. as a general rule the allowable derating factor is equal to the square of the scaling factor. note: the interline period is not guaranteed consistent for all derating ratios. this means the host capture system must be able to cope with use of the sync signals or embedded codes rather than relying on fixed line counts. defect correction this function runs a defect correction filter over the data in order to remove defects from the final output. this function has been optimized to attain the minimum level of defects from the system and does not need to be adjusted. nora the noise reduction module implements an algorithm based on the human-visual system and adaptive pixel filtering that reduces perceived noise in an image whilst maintaining areas of high definition. demosaic this module performs an interpolation on the bayer data from the sensor array to produce a srgb data. at this point an anti-alias filter is applied. anti-zipper the demosaic process produces an rgb frame with a noise signal at pixel frequency. to remove this artefact an anti-zipper filter is employed. sharpening this module increases the high frequency content of the image in order to compensate for the low-pass filtering effects of the previous modules. gamma this module applies a programmable gain curve to the output data. it is user adjustable.
system architecture vl6624/VS6624 12/106 yuv conversion this module performs color space conversion from rgb to yuv. it is used to control the contrast and color saturation of the output image as well as the fade to black feature. dither this module is used to reduce the contouring effect seen in rgb images with truncated data. output formatter this module controls the embedded codes which are inserted into the data stream to allow the host system to synchronize with the output data. it also controls the optional hsync and vsync output signals. 3.3 microprocessor functions the microprocessor inside the vl6624/VS6624 performs the following tasks: host communication handles the i2c communication with the host processor. video pipe configuration configures the video pipe modules to produce the output required by the host. automatic exposure control in normal operation the vl6624/VS6624 determines the appropriate exposure settings for a particular scene and outputs correctly exposed images. flicker cancellation the 50/60hz flicker frequency present in the lighting (due to fluorescent lighting) can be cancelled by the system. automatic white balance the microprocessor adjusts the gains applied to the individual color channels in order to achieve a correctly color balanced image. frame rate control VS6624 contains a firmware based programmable timing generator. this automatically designs internal video timings, pll multipliers, clock dividers etc. to achieve a target frame rate with a given input clock frequency. optionally an automatic frame rate controller can be enabled. this system examines the current exposure status, integration time and gain and adapts the frame rate based on that. this function is typically useful in low-light scenarios where reducing the frame rate extends the useful integration period. this reduces the need for the application of analog and digital gain and results in better quality images. dark calibration the microprocessor uses information from special dark lines within the pixel array to apply an offset to the video data and ensure a consistent ?black? level. active noise management the microprocessor is able to modify certain video pipe functions according to the current exposure settings determined by the automatic exposure controller. the main purpose of this is to improve the noise level in the system under low lighting conditions. functions which ?strength? is reduced under low lighting conditions (e.g. sharpening) are controlled by ?dampers?. functions which ?strength? is increased under low lighting conditions are controlled by ?promoters?. the fade to black operation is also controlled by the microprocessor
vl6624/VS6624 operational modes 13/106 4 operational modes vl6624/VS6624 has a number of operational modes. the power down mode is entered and exited by driving the hardware ce signal. transitions between all other modes are initiated by i2c transactions from the host system or automatically after time-outs. figure 2. state machine at power -up and user mode transitions power down/up the power down state is entered from all other modes when ce is pulled low or the supplies are removed. during the power-down state (ce = logic 0) the internal digital supply of the vl6624/VS6624 is shut down by an internal switch mechanism. this method allows a very low power-down current value. the device input / outputs are fail-safe, and consequently can be considered high impedance. supplies off standby power-down ce pin low ce pin pause mode supplies turned-off supplies turned-on & ce pin low supplies turned-off 1 stop mode run mode high state machine at power-up i 2 c controlled user mode transitions uninitialised - flashgun note; depending on the snapshot exit transition settings the device will revert to run or pause state automatically after snapshot it is possible to enter any of the user modes direct from the uninitialised state via an i2c command system state changes host initiated state changes snapshot
operational modes vl6624/VS6624 14/106 during the power-up sequence (ce = logic 1) the digital supplies must be on and stable. the internal digital supply of the vl6624/VS6624 is enabled by an internal switch mechanism. all internal registers are reset to default values by an internal power on reset cell. figure 3. power up sequence standby mode the vl6624/VS6624 enters standby mode when the ce pin on the device is pulled high. power consumption is very low, most clocks inside the device are switched off. in this state i2c communication is possible when clk is present and when the microprocessor is enabled. all registers are reset to their default values. the device i/o pins have a very high- impedance. uninitialised = raw the initialize mode is defined as supplies present, the ce signal is logic 1 and the microcontroller clock has been activated. during initialize mode the device firmware may be patched. this state is provided as an intermediary configuration state and is not central to regular operation of the device. the analogue video block is powered down, leading to a lower global consumption stop mode this is a low power mode. the analogue section of the vl6624/VS6624 is switched off and all registers are accessed over the i2c interface. a run command received in this state automatically sets a transition through the pause state to the run mode. note: the device must be in stop mode to adjust output size. the analogue video block is powered down, leading to a lower global consumption. ce clk avdd (2.8v) vdd (1.8v/2.8v) sda scl t1 t2 t3 t4 t1 >= 0ns t2 >= 0ns t3 >= 0ns t4 >= tbc ms constraints: t5 low level command: enable clocks setup commands t5 >= tbc ms standby power down uninitialised mode
vl6624/VS6624 operational modes 15/106 pause mode in this mode all vl6624/VS6624 clocks are running and all registers are accessible but no data is output from the device. the device is ready to start streaming but is halted. this mode is used to set up the required output format before outputting any data. the analogue video block is powered down, leading to a lower global consumption note: the powermanagement register can be adjusted in pause mode but has no effect until the next run to pause transition. 4.1 streaming modes run mode this is the fully operational mode. in running mode the device outputs a continuous stream of images, according to the set image format parameters and frame rate control parameters. the image size is derived through downscaling of the sxga image from the pixel array. viewlive this feature allows different sizes, formats and reconstruction settings to be applied to alternate frames of data, while in run mode. snapshot mode the device can be configured to output a single frame according to the size, format and reconstruction settings in the relevant pipe setup bank. in normal operation this frame will be output, once the exposure, white balance and dark-cal systems are stable. to reduce the latency to output, the user may manually override the stability flags. the snapshot mode command can be issued in either run or stop mode and the device will automatically return previous state after the snapshot is taken. the snapshot mode must not be entered into while viewlive is selected. flashgun mode in flashgun mode, the array is configured for use with an external flashgun. a flash is triggered and a single frame of data is output and the device automatically switches to pause mode. VS6624 supports the following flashgun configurations: torch mode - user can manually switch on/off the fso io pin via a register setting. independent of mode. pulsed mode - the flash output is synchronized to the image stream. there are two options available: ? pulsed flash with snapshot. device outputs a single frame synchronized to flash. ? pulsed flash with viewfinder. device outputs a flash pulse synchronized to a single frame in the image stream. ? in the pulsed mode there are two possible pulse configurations: ? single pulse during the interframe period when all image lines are exposed. this is suitable for scr and igbt flash configurations. the falling edge of the pulse can be programmed to vary the width of the pulse. ? single pulse over entire integration period of frame. this is suitable for led flash configurations.
operational modes vl6624/VS6624 16/106 4.2 mode transitions transitions between operating modes are normally controlled by the host by writing to the host interface manager control register. some transitions can occur automatically after a time out. if there is no activity in the pause state then an automatic transition to the stop state occurs. this functionality is controlled by the power management register, writing 0xff disables the automatic transition to stop. the users control allows a transition between stop and run, at the state level the system will transition through a pause state.
vl6624/VS6624 clock control 17/106 5 clock control input clock the VS6624 requires provision of an external reference clock. the external clock should be a dc coupled square wave. the clock signal may have been rc filtered. the clock input is fail-safe in power down mode. the vl6624/VS6624 contains an internal pll allowing it to produce accurate frame rates from a wide range of input clock frequencies. the allowable input range is from 6.5mhz to 54mhz. the input clock frequency must be programmed in the registers. to program an input frequency of 6.5 mhz, the numerator can be set to 13 and the denominator to 2. the default input frequency is 12 mhz. the VS6624 may be configured as a master or slave device. in normal (master operation) the input clock can be a different frequency to the output pclk and all output clock configuration is based on the internal pll. in slave configuration, the input clock is the same frequency and phase as the output pclk. i.e. parallel output data is synchronized to the input clock.
frame control vl6624/VS6624 18/106 6 frame control sensor mode control the VS6624 device can operate it?s sensor array in three modes controlled by register sensormode within mode setup . sensormode_sxga - the full array is readout and the max frame rate achievable is 15fps sensormode_vga_analogue binning - the full array operates and a technique of analogue binning is used to output vga at up to 30fps sensormode_vga_subsampled - the array is sub-sampled to output vga at up to 30fps image size an output frame consists of a number of active lines and a number of interframe lines. each line consists of embedded line codes (if selected), active pixel data and interline blank data. note that by default the interline blanking data is not qualified by the pclk and therefore is not captured by the host system. the image size can be either the full output from the sensor, depending on sensor mode, or a scaled output, the output image size can be chosen from one of 7 pre-selected sizes or a manual image size can be input. cropping module the vl6624/VS6624 contains a cropping module which can be used to define a window of interest within the full sxga array size. the user can set a start location and the required output size. figure 4 shows the example with pipe setup bank0.
vl6624/VS6624 frame control 19/106 figure 4. crop controls zoom it is possible to zoom between the sensor size selected and the output size (if the output size selected equals the sensor mode size then no zoom can take place). the zoom step size in both the horizontal and vertical directions are selectable and zoom controlled with the commands zoom_in, zoom_out and zoom_stop. pan it is possible to pan left, right, up and down when the output size selected is smaller than the sensor size selected. (if the output size selected equals the sensor mode size then no pan can take place). the pan step size in both the horizontal and vertical directions are selectable. frame rate control the vl6624/VS6624 features an extremely flexible frame rate controller. using registers uwdesiredframerate_num, and uwdesiredframerate_den any desired frame rate between 2 and 15 fps can be selected for the sxga sensor mode and between 1 and 30fps for a vga sensor mode. to program a required frame rate of 7.5 fps the numerator can be set to 15 and the denominator to 2. cropped roi ffov sensor array horizontal size sensor array vertical size uwmanualcrophorizontalstart uwmanualcropverticalstart uwmanualcropverticalsize uwmanualcrophorizontalsize
frame control vl6624/VS6624 20/106 horizontal mirror and vertical flip the image data output from the vl6624/VS6624 can be mirrored horizontally or flipped vertically (or both). video pipe setup the VS6624 has a single video pipe, the control of this pipe can be loaded from either of two possible setups pipesetupbank0 and pipesetupbank1; pipe setup bank0 and pipe setup bank1 , control the operations shown below, image size zoom control pan control crop control image format (yuv 4:2:2, rgb565, etc....) image controls (contrast, color saturation, horizontal and vertical flip) pipe 0 rgb to yuv matrix manual control and pipe 1 rgb to yuv matrix manual control , allow different rgb to yuv matrixes to be used for each pipe setup, pipe 0 gamma manual control and pipe 1 gamma manual control , allow different gamma settings to be used for each pipe setup. context switching in normal operation, it is possible to control which pipe setup bank is used and to switch between banks without the need to stop streaming, the change will occur at the next frame boundary after the change to the register has been made. for example this function allows the vl6624/VS6624 to stream an output targeting a display (e.g. qqvga rgb 444) then switch to capture an image (e.g. sxga yuv 4:2:2) with no need to stop streaming or enter any other operating mode. it is important to note the output size selected for both pipe setups must be appropriate to the sensor mode used, i.e. to configure pipesetupbank0 to qqvga and pipesetupbank1 to sxga the sensor mode must be set to sxga. the register mode setup allows selection of the pipe setup bank, by default the pipe setup bank 0 is used.
vl6624/VS6624 frame control 21/106 viewlive operation viewlive is an option which allows a different pipe setup bank to be applied to alternate frames of the output data. the controls for viewlive function are found in the register bank where the fenable register allows the host to enable or disable the function and the binitialpipesetupbank register selects which pipe setup bank is output first. when viewlive is enabled the output data switches between pipe setup bank0 and pipe setup bank1 on each alternate frame. figure 5. viewlive frame output format interframe blanking active video pipe setup bank0 interline blanking interline blanking interframe blanking active video pipe setup bank1 frame output
output data formats vl6624/VS6624 22/106 7 output data formats the vl6624/VS6624 supports the following data formats: yuv4:2:2 yuv4:0:0 rgb565 rgb444 (encapsulated as 565) rgb444 (zero padded) bayer 10-bit bayer 8-bit the required data format is selected using the bdatafomat control found in the pipe setup bank registers. the various options available for each format are controlled using the brgbsetup and byuvsetup registers found in the output formatter control registers. line / frame blanking data the values which are output during line and frame blanking are an alternating pattern of 0x10 and 0x80 by default. these values may be changed by writing to the blankdata_msb and blankdata_lsb registers in the output formatter control bank. yuv 4:2:2 data format yuv 422 data format requires 4 bytes of data to represent 2 adjacent pixels. itu601-656 defines the order of the y, cb and cr components as shown in figure 6 . figure 6. standard y cb cr data order the vl6624/VS6624 byuvsetup register can be programmed to change the order of the components as follows: 0 0 0 0 x y eav code start of digital active line hsync signal 8 0 1 0 f f cb cr yy cb cr y y cb cr yy 4-data packet
vl6624/VS6624 output data formats 23/106 figure 7. y cb cr data swapping options register 0x2294 byuvsetup yuv 4:0:0 the itu protocol allows the encapsulation of various data formats over the link. the following data formats are also proposed encapsulated in itu601-656 protocol: yuv 4:0:0 - luminance data channel this is done as described in figure 8 . in this output mode the output data per pixel is a single byte. therefore the output pclk and data rate is halved. it is possible to reverse the overall bit order of the component through a register programming. note: false synchronization codes are avoided in the lsbyte by adding or subtracting a value of one, dependent on detection of a 0 code or 255 code respectively. figure 8. yuv 4:0:0 format encapsulated in itu stream see output formatter control for user interface control of output data formats. y first cb first 1 0 1 1 0 1 0 0 cb cr yy in 4-byte data packet components order 1st 2nd 3rd 4th cb y cr y cb cr yy cb y cr y default bit [1] bit [0] f f 0 0 0 0 x y eav code start of digital active line d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 8 d 9 yuv4:0:0 pixel1 f f 0 0 0 0 x y where: pixel n = y n [7:0] pixel2 pixel3 pixel4 pixel5 pixel6 pixel7 pixel8 pixel9 pixel10 .................. ..................
output data formats vl6624/VS6624 24/106 rgb and bayer 10 bit data formats the vl6624/VS6624 can output data in the following formats: rgb565 rgb444 (encapsulated as rgb565) rgb444 (zero padded) bayer 10-bit note: pixels in bayer 10-bit data output are defect corrected, correctly exposed and white balanced. any or all of these functions can be disabled. in each of these modes 2 bytes of data are required for each output pixel. the encapsulation of the data is shown in ta b l e 9 . figure 9. rgb and bayer data formats (2) rgb 444 packed as rgb565 0 1 2 3 4 5 6 7 bit r 3 r 4 r 2 r 1 g 5 r 0 g 4 g 3 second byte 0 1 2 3 4 5 6 7 bit g 1 g 2 g 0 b 4 b 2 b 3 b 1 b 0 (1) rgb565 data packing first byte 0 1 2 3 4 5 6 7 bit r 2 r 3 r 1 r 0 g 3 1 g 2 g 1 second byte 0 1 2 3 4 5 6 7 bit 1 g 0 0 b 3 b 1 b 2 b 0 1 first byte (3) rgb 444 zero padded 0 1 2 3 4 5 6 7 bit 0 0 0 0 r 2 r 3 r 1 r 0 second byte 0 1 2 3 4 5 6 7 bit g 2 g 3 g 1 g 0 b 2 b 3 b 1 b 0 first byte (4) bayer 10-bit 0 1 2 3 4 5 6 7 bit 0 1 1 0 0 1 b 9 b 8 second byte 0 1 2 3 4 5 6 7 bit b 6 b 7 b 5 b 4 b 2 b 3 b 1 b 0 first byte
vl6624/VS6624 output data formats 25/106 manipulation of rgb data it is possible to modify the encapsulation of the rgb data in a number of ways: swap the location of the red and blue data reverse the bit order of the individual color channel data reverse the order of the data bytes themselves dithering an optional dithering function can be enabled for each rgb output mode to reduce the appearance of contours produced by rgb data truncation. this is enabled through the dithercontrol register. bayer 8-bit the itu protocol allows the encapsulation of various data formats over the link. the following data formats are also proposed encapsulated in itu601-656 protocol: raw 8-bit bayer truncated from 10-bit dpcm encoded from 10-bit this is done as described in figure 10 . in this output mode the output data per pixel is a single byte. therefore the output pclk and data rate is halved. it is possible to reverse the overall bit order of the individual bayer pixels through a register programming. note: false synchronization codes are avoided in the lsbyte by adding or subtracting a value of one, dependent on detection of a 0 code or 255 code respectively. figure 10. bayer 8 output f f 0 0 0 0 x y eav code start of digital active line d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 8-bit bayer pixel1 f f 0 0 0 0 x y where: lsb n = bayer n [7:0] l s b 0 l s b 1 l s b 2 l s b 3 l s b 4 l s b 5 l s b 6 l s b 7 l s b 8 l s b 9 l s b 10 l s b 11 pixel3 pixel5 pixel7 pixel9 pixel11
data synchronization methods vl6624/VS6624 26/106 8 data synchronization methods external capture systems can synchronize with the data output from vl6624/VS6624 in one of two ways: 1. synchronization codes are embedded in the output data 2. via the use of two additional synchronization signals: vsync and hsync both methods of synchronization can be programmed to meet the needs of the host system. embedded codes the embedded code sequence can be inserted into the output data stream to enable the external host system to synchronize with the output frames. the code consists of a 4-byte sequence starting with 0xff, 0x00, 0x00. the final byte in the sequence depends on the mode selected. two types of embedded codes are supported by the vl6624/VS6624: mode 1 (itu656) and mode 2. the bsynccodesetup register is used to select whether codes are inserted or not and to select the type of code to insert. when embedded codes are selected each line of data output contains 8 additional clocks: 4 before the active video data and 4 after it. prevention of false synchronization codes the vl6624/VS6624 is able to prevent the output of 0xff and/or 0x00 data from being misinterpreted by a host system as the start of synchronization data. this function is controlled the bcodecheckenable register. mode 1 (itu656 compatible) the structure of an image frame with itu656 codes is shown in figure 11 .
vl6624/VS6624 data synchronization methods 27/106 figure 11. itu656 frame structure with even codes the synchronization codes for odd and even frames are listed in ta b l e 3 and ta bl e 4 . by default all frames output from the vl6624/VS6624 are even. it is possible to set all frames to be odd or to alternate between odd and even using the synccodesetup register in the output formatter control register bank. table 3. itu656 embedded synchronization code definition (even frames) name description 4-byte sequence sav line start - active ff 00 00 80 eav line end - active ff 00 00 9d sav (blanking) line start - blanking ff 00 00 ab eav (blanking) line end - blanking ff 00 00 b6 table 4. itu656 embedded synchronization code definition (odd frames) name description 4-byte sequence sav line start - active ff 00 00 c7 eav line end - active ff 00 00 da sav (blanking) line start - blanking ff 00 00 ec eav (blanking) line end - blanking ff 00 00 f1 eav sav frame of image data line 1 line 480 frame blanking period line blanking period 9d 80 eav b6 sav ab
data synchronization methods vl6624/VS6624 28/106 mode 2 the structure of a mode 2 image frame is shown figure 12 . figure 12. mode 2 frame structure (vga example) for mode 2, the synchronization codes are as listed in ta b l e 5 . table 5. mode 2 - embedded synchronization code definition name description 4-byte sequence ls line start ff 00 00 00 le line end ff 00 00 01 fs frame start ff 00 00 02 fe frame end ff 00 00 03 le ls frame of image data line 1 line 480 frame blanking period line blanking period fe fs
vl6624/VS6624 data synchronization methods 29/106 mode 2 logical dma channels the purpose of logical channels is to separate different data flows which are interleaved in the data stream, in the case of the VS6624 this allows the identification of the pipe setup bank used for an image frame. the dma channel identifier number is directly encoded in the 4-byte mode2 embedded sync codes. the receiver can then monitor the dma channel identifier and de-multiplex the interleaved video streams to their appropriate dma channel. the bchannelid register can have the value 0 to 6. the dma channel identifier must be fully programmable to allow the host to configure which dma channels the different video data stream use. logical channel control the channel identifier is a part of mode2 synchronization code, upper four bits of last byte of synchronization code. figure 13. illustrates the synchronization code with logical channel identifiers. figure 13. mode 2 frame structure (vga example) vsync and hsync the vl6624/VS6624 can provide two programmable hardware synchronization signals: vsync and hsync. the position of these signals within the output frame can be programmed by the user or an automatic setting can be used where the signals track the active video portion of the output frame regardless of its size. horizontal synchronization signal (hsync) the hsync signal is controlled by the bhsyncsetup register. the following options are available: enable/disable select polarity all lines or active lines only manual or automatic ff0000dclc dma channel number valid channels = 0 to 6 line code 0x0 = line start 0x1 = line end 0x2 = frame start 0x3 = frame end 32-bit embedded mode 2 sync code
data synchronization methods vl6624/VS6624 30/106 in automatic mode the hsync signal envelops all the active video data on every line in the output frame regardless of the programmed image size. line codes (if selected) fall outside the hsync envelope as shown in figure 14 . figure 14. hsync timing example if manual mode is selected then the pixel positions for hsync rising edge and falling edge are programmable. the pixel position for the rising edge of hsync is programmed in the bhsyncrising registers. the pixel position for the falling edge of hsync is programmed in the bhsyncfalling registers. vertical synchronization (vsync) the vsync signal is controlled by the bsyncsetup register. the following options are available: enable/disable select polarity manual or automatic in automatic mode the vsync signal envelops all the active video lines in the output frame regardless of the programmed image size as shown in figure 15 . ff sav code eav code active video data hsync=1 eav code blanking data hsync=0 00 00 xy 80 10 80 10 80 10 80 10 00 00 xy ff d0 d1 d2 d3 d0 d1 d2 d3 d2 d3 ff 00 00 xy
vl6624/VS6624 data synchronization methods 31/106 figure 15. vsync timing example if manual mode is selected then the line number for vsync rising edge and falling edge is programmable. the rising edge of vsync is programmed in the bvsyncrisingline registers, the pixel position for vsync rising edge is programmed in the bvsyncrisingpixel registers. similarly the line count for the falling edge position is specified in the bvsyncfallingline registers, and the pixel count is specified in the bvsyncfallingpixel registers. pixel clock (pclk) the pclk signal is controlled by the output formatter control register. the following options are available: enable/disable select polarity select starting phase qualify/don?t qualify embedded synchronization codes enable/disable during horizontal blanking blanking blanking v=1 v=0 v=1 v=0 vsync active video active video
data synchronization methods vl6624/VS6624 32/106 figure 16. qclk options the yuv, rgb and bayer timings are represented on figure 17 , with the associated qualifying pclk clock. the output clock rate is effectively halved for the bayer 8-bit and yuv4:0:0 modes where only one byte of output data is required per pixel. figure 17. qualification clock d0 d1 d2 data negative edge pclk negative edge positive edge positive edge none-active level - low none-active level - high y n cb n,n+1 y n+1 cr n,n+1 ycbcr data[7:0] data[7:0] rgb565 cb n+2,n+3 rgb444 pix0_lsb pix0_msb pix1_lsb pix1_msb pix2_lsb data[7:0] bayer 10-bit pix0_lsb pix0_msb pix1_lsb pix1_msb pix2_lsb data[7:0] bayer 8-bit pix0 pix1 pix2 data[7:0] yuv 4:0:0 pix0 pix1 pix2 16-bit data output formats - 2 bytes per pixel 8-bit data output formats- 1 byte per pixel pclk pclk pclk pclk pclk
vl6624/VS6624 data synchronization methods 33/106 master / slave operation of plck in normal operation VS6624 acts as a master. pclk is independent of the input clock frequency and does not have a determined phase relation to the input clock. in slave operation the input clock frequency is the same as the output clock frequency and the output data is guaranteed with a certain phase relationship to the input clock. internally, the VS6624 uses clocks generated from the internal pll, but a retiming stage is used to re- sync the output to the input clock. in this output mode, derating is not possible.
getting started vl6624/VS6624 34/106 9 getting started initial power up before any communication is possible with the vl6624/VS6624 the following steps must take place: 1. apply vdd (1.8v or 2.8v) 2. apply avdd (2.8v) 3. apply an external clock (6.5mhz to 54mhz) 4. assert ce line high these steps can all take place simultaneously. after these steps are complete a delay of 200 s is required before any i2c communication can take place, see figure 3: power up sequence . minimum startup command sequence 1. enable the microprocessor - before any commands can be sent to the vl6624/VS6624, the internal microprocessor must be enabled by writing the value 0x02 to the microenable register 0xc003 found in the low level control registers section. 2. enable the digital i/o - after power up the digital i/o of the vl6624/VS6624 is in a high- impedance state (?tri-state?). the i/o are enabled by writing the value 0x01 to the dio_enable register 0xc044 found in the low level control registers section. 3. the user can then program the system clock frequency and setup the required output format before placing the vl6624/VS6624 in run mode by writing 0x02 to the host interface manager control register 0x0180. the above three commands represent the absolute minimum required to get video data output. the default configuration results in an output of sxga, 15 fps, yuv data format with itu embedded codes requiring a external clock frequency of 12mhz. in practice the user is likely to require to write some additional setup information prior to receive the required data output.
vl6624/VS6624 host communication - i2c control interface 35/106 10 host communication - i2c control interface the interface used on the vl6624/VS6624 is a subset of the i2c standard. higher level protocol adaptations have been made to allow for greater addressing flexibility. this extended interface is known as the v2w interface. 10.1 protocol a message contains two or more bytes of data preceded by a start (s) condition and followed by either a stop (p) or a repeated start (sr) condition followed by another message. stop and start conditions can only be generated by a v2w master. after every byte transferred the receiving device must output an acknowledge bit which tells the transmitter if the data byte has been successfully received or not. the first byte of the message is called the device address byte and contains the 7-bit address of the v2w slave to be addressed plus a read/write bit which defines the direction of the data flow between the master and the slave. the meaning of the data bytes that follow device address changes depending whether the master is writing to or reading from the slave. figure 18. write message for the master writing to the slave the device address byte is followed by 2 bytes which specify the 16-bit internal location (index) for the data write. the next byte of data contains the value to be written to that register index. if multiple data bytes are written then the internal register index is automatically incremented after each byte of data transferred. the master can send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or sends a repeated start (sr). figure 19. read message for the master reading from the slave the device address is followed by the contents of last register index that the previous read or write message accessed. if multiple data bytes are read then the internal register index is automatically incremented after each byte of data ?0? (write) s dev addr r/w a 2 index bytes data p a/a data a n data byte a data from master to slave from slave to master ?1? (read) s dev addr r/w a data p a data a 1 or more data byte from master to slave from slave to master
host communication - i2c control interface vl6624/VS6624 36/106 read. a read message is terminated by the bus master generating a negative acknowledge after reading a final byte of data. a message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation. 10.2 detailed overview of the message format figure 20. detailed overview of message format the v2w generic message format consists of the following sequence sda scl s or sr 12 789 sr or p msb lsb start or repeated start condition ack signal from slave stop or repeated start condition device address 12 789 msb lsb s (sr) 7-bit device address r/w a a (a ) 8-bit data p (sr) data byte from transmitter r/w =0 - master r/w =1 - slave ack signal from receiver r/w bit 0 - write 1 - read sr p 1 2 3 4 5 6
vl6624/VS6624 host communication - i2c control interface 37/106 1. master generates a start condition to signal the start of new message. 2. master outputs, ms bit first, a 7-bit device address of the slave the master is trying to communicate with followed by a r/w bit. a) r/w = 0 then the master (transmitter) is writing to the slave (receiver). b) r/w = 1 the master (receiver) is reading from the slave (transmitter). 3. the addressed slave acknowledges the device address. 4. data transmitted on the bus a) when a write is performed then master outputs 8-bits of data on sda (ms bit first). b) when a read is performed then slave outputs 8-bits of data on sda (ms bit first). 5. data receive acknowledge a) when a write is performed slave acknowledges data. b) when a read is performed master acknowledges data. repeat 4 and 5 until all the required data has been written or read. minimum number of data bytes for a read =1 (shortest message length is 2-bytes). the master outputs a negative acknowledge for the data when reading the last byte of data. this causes the slave to stop the output of data and allows the master to generate a stop condition. 6. master generates a stop condition or a repeated start. figure 21. device addresses 0 0 1 0 0 0 0 r/w 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 sensor address sensor write address 20 h sensor read address 21 h
host communication - i2c control interface vl6624/VS6624 38/106 10.3 data valid the data on sda is stable during the high period of scl. the state of sda is changed during the low phase of scl. the only exceptions to this are the start (s) and stop (p) conditions as defined below. (see i2c slave interface for full timing specification). figure 22. sda data valid 10.4 start (s) and stop (p) conditions a start (s) condition defines the start of a v2w message. it consists of a high to low transition on sda while scl is high. a stop (p) condition defines the end of a v2w message. it consists of a low to high transition on sda while scl is high. after stop condition the bus is considered free for use by other devices. if a repeated start (sr) is used instead of a stop then the bus stays busy. a start (s) and a repeated start (sr) are considered to be functionally equivalent. figure 23. start and stop conditions sda scl data line stable data valid data change data line stable data valid start condition stop condition s p sda scl
vl6624/VS6624 host communication - i2c control interface 39/106 10.5 acknowledge after every byte transferred the receiver must output an acknowledge bit. to acknowledge the data byte receiver pulls sda during the 9th scl clock cycle generated by the master. if sda is not pulled low then the transmitter stops the output of data and releases control of the bus back to the master so that it can either generate a stop or a repeated start condition. figure 24. data acknowledge 10.6 index space communication using the serial bus centres around a number of registers internal to the either the sensor or the co-processor. these registers store sensor status, set-up, exposure and system information. most of the registers are read/write allowing the receiving equipment to change their contents. others (such as the chip id) are read only. the internal register locations are organized in a 64k by 8-bit wide space. this space includes ?real? registers, sram, rom and/or micro controller values. s 12 89 start condition negative acknowledge (a ) acknowledge (a) clock pulse for acknowledge sda data transmitter output by sda data receiver output by scl clock from master
host communication - i2c control interface vl6624/VS6624 40/106 figure 25. internal register index space 10.7 types of messages this section gives guidelines on the basic operations to read data from and write data to vl6624/VS6624. the serial interface supports variable length messages. a message contains no data bytes or one data byte or many data bytes. this data can be written to or read from common or different locations within the sensor. the range of instructions available are detailed below. single location, single byte data read or write. write no data byte. only sets the index for a subsequent read message. multiple location, multiple data read or write for fast information transfers. any messages formats other than those specified in the following section should be considered illegal. 0 1 2 3 4 65532 65533 65534 65535 16-bit index / 8-bit data format 64k by 8-bit wide index space (valid addresses 0-65535) 130 129 128 127 126 125 8 bits
vl6624/VS6624 host communication - i2c control interface 41/106 10.8 random location, single data write for the master writing to the slave the r/w bit is set to zero. the register index value written is preserved and is used by a subsequent read. the write message is terminated with a stop condition from the master. figure 26. random location, single write 10.9 current location, single data read for the master reading from the slave the r/w bit is set to one. the register index of the data returned is that accessed by the previous read or write message. the first data byte returned by a read message is the contents of the internal index value and not the index value. this was the case in older v2w implementations. note that the read message is terminated with a negative acknowledge (a ) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. this is because if the data sent by the slave is all zeros, the sda line cannot rise, which is part of the stop condition. figure 27. current location, single read s dev addr r/w a data p a/a data a data a index[7:0] data[7:0] index[15:8] previous index value, k index m 16-bit index, 8-bit data, random location, single data write index[15:0] value, m data[7:0] from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = negative acknowledge ?0? (write) data data[7:0] data[7:0] s dev addr r/w a ?1? (read) p a previous index value, k 16-bit index, 8-bit data current location, single data read from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = negative acknowledge
host communication - i2c control interface vl6624/VS6624 42/106 10.10 random location, single data read when a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written first, specifying the index. the read message then completes the message sequence. to avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the write and read messages. as mentioned in the previous example, the read message is terminated with a negative acknowledge (a ) from the master. figure 28. 16-bit index, 8-bit data random index, single data read 10.11 multiple location write for messages with more than 1 data byte the internal register index is automatically incremented for each byte of data output, making it possible to write data bytes to consecutive adjacent internal registers without having to send explicit indexes prior to sending each data byte. figure 29. 16-bit index, 8-bit data multiple location write ?0? (write) s dev addr r/w a data a data a index[7:0] index[15:0] value, m index[15:8] data data[7:0] data[7:0] sr dev addr r/w a ?1? (read) p a previous index value, k index m no data write data read a = acknowledge a = negative acknowledge s = start condition sr = repeated start p = stop condition from slave to master from master to slave ?0? (write) s dev addr r/w a data p a/a data a data a index[7:0] data[7:0] index[15:0] value, m data[7:0] index[15:8] data a data[7:0] data[7:0] n bytes of data previous index value, k index m index (m + n - 1) a = acknowledge a = negative acknowledge s = start condition sr = repeated start p = stop condition from slave to master from master to slave
vl6624/VS6624 host communication - i2c control interface 43/106 10.12 multiple location read stating from the current location in the same manner to multiple location writes, multiple locations can be read with a single read message. figure 30. multiple location read data data[7:0] data[7:0] s dev addr r/w a ?1? (read) data p a a data[7:0] data[7:0] n bytes of data index k+1 index (k + n - 1) data data[7:0] data[7:0] a previous index value, k 16-bit index, 8-bit data multiple location read a = acknowledge a = negative acknowledge s = start condition sr = repeated start p = stop condition from slave to master from master to slave
host communication - i2c control interface vl6624/VS6624 44/106 10.13 multiple location read starting from a random location figure 31. multiple location read starting from a random location ?0? (write) s dev addr r/w a data a data a index[7:0] index[15:0] value, m index[15:8] data data[7:0] data[7:0] sr dev addr r/w a ?1? (read) data p a a data[7:0] data[7:0] n bytes of data from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = negative acknowledge previous index value, k index (m + n - 1) index m no data write data read 16-bit index, 8-bit data random index, multiple data read
vl6624/VS6624 register map 45/106 11 register map the vl6624/VS6624 i2c write address is 0x20. to read or write to registers other than those in low level control registers section the device must be switched on, this is done by writing 0x02 to 0xc003. information on initial power up for the device can be found in the section 9: getting started . all i2c locations contain an 8-bit byte. however, certain parameters require 16 bits to represent them and are therefore stored in more than 1 location. note: for all 16 bit parameters the msb register must be written before the lsb register. the data stored in each location can be interpreted in different ways as shown below. register contents represent different data types as described in ta b l e 6 . float number format float 900 is used in st co-processors to represent floating point numbers in 2 bytes of data. it conforms to the following structure: bit[15] = sign bit (1 represents negative) bit[14:9] = 6 bits of exponent, biased at decimal 31 bit[8:0] = 9 bits of mantissa to convert a floating point number to float 900, use the following procedure: represent the number as a binary floating point number. normalize the mantissa and calculate the exponent to give a binary scientific representation of 1.xxxxxxxxx * 2^y. the x symbols should represent 9 binary digits of the mantissa, round or pad with zeros to achieve 9 digits in total. remove the leading 1 from the mantissa as it is redundant. to calculate the y value bias the exponent by adding to 31 decimal then converting to binary. the data can then be placed in the structure above. table 6. data type data type description byte single field register 8 bit parameter uint_16 multiple field registers - 16 bit parameter flag_e bit 0 of register must be set/cleared coded coded register - function depends on value written float float value
register map vl6624/VS6624 46/106 example convert -0.41 to float 900 convert the fraction into binary by successive multiplication by 2 and removal of integer component 0.41 * 2 = 0.82 0 0.82 * 2 = 1.64 1 0.64 * 2 = 1.28 1 0.28 * 2 = 0.56 0 0.56 * 2 = 1.12 1 0.12 * 2 = 0.24 0 0.24 * 2 = 0.48 0 0.48 * 2 = 0.96 0 0.96 * 2 = 1.92 1 0.92 * 2 = 1.84 1 0.84 * 2 = 1.68 1 0.68 * 2 = 1.36 1 0.36 * 2 = 0.72 0 this gives us -0.0110100011110. we then normalize by moving the decimal point to give - 1.10100011110 * 2^-2. the mantissa is rounded and the leading zero removed to give 101001000. we add the exponent to the bias of 31 that gives us 29 or 11101. a leading zero is added to give 6 bits 011101. the sign bit is set at 1 as the number is negative. this gives us 1011 1011 0100 1000 as our float 900 representation or bb48 in hex. to convert the encoded representation back to a decimal floating point, we can use the following formula. real is = (-1)^sign * ((512+mantissae)>> 9) * 2^(exp-31) thus to convert bb48 back to decimal, the following procedure is followed: note that >>9 right shift is equal to division by 2^9. sign = 1 exponent = 11101 (29 decimal) mantissa = 101001000 (328 decimal) this gives us: real = (-1)^1 * ((512+328)/2^9) * 2^(29-31) real = -1 * (840/512) * 2^(-2) real = -1 * 1.640625 * 0.25 real = -0.41015625 when compared to the original -0.41, we see that some rounding errors have been introduced.
vl6624/VS6624 register map 47/106 low level control registers note: the default values for the above registers are true when the device is powered on, ext. clk input is present and the ce pin is high. all other registers can be read when the microenable register is set to 0x02. table 7. low-level control registers index lowlevelcontrolregisters (1) 1. can be controlled in all stable states. 0xc003 microenable default value 0x1c purpose used to power up the device ty p e coded possible values <0x1c> initial state after low to high transition of ce pin <0x02> power enable for all mcu clock- start device 0xc044 dio_enable default value 0x00 purpose enables the digital i/o of the device ty p e coded possible values <0> io pins in a high impedance state ?tri-state? <1> io pins enabled
register map vl6624/VS6624 48/106 user interface map device parameters [read only] host interface manager control table 8. device parameters [read only] index deviceparameters [read only] (1) 0x0001 (msbyte) 0x0002 (lsbyte) uwdeviceid purpose device id e.g. 624 ty p e uint 0x0004 bfirmwarevsnmajor ty p e byte 0x0006 bfirmwarevsnminor ty p e byte 0x0008 bpatchvsnmajor ty p e byte 0x000a bpatchvsnminor ty p e byte 1. can be accessed in all stable state. table 9. host interface manager control index hostinterfacemanagercontrol (1) 0x0180 busercommand default value <0> uninitialised purpose user level control of operating states ty p e coded possible values <0> uninitialised - powerup default <1> boot - the boot command will identify the sensor & setup low level handlers <2> run - stream video <3> pause- stop video streaming <4> stop - low power mode, analogue powered down <3> snapshot- grab one frame at correct exposure without flashgun <6> flashgun - grab one frame at correct exposure for flashgun 1. can be controlled in all stable states
vl6624/VS6624 register map 49/106 host interface manager status run mode control table 10. host interface manager status [read only] index hostinterfacemanagerstatus [read only] (1) 0x0202 bstate default value <16>_raw purpose the current state of the mode manager. ty p e coded possible values <16>_raw - default powerup state. <33> waiting_for_boot - waiting for modemanager to signal boot event. <34> paused - booted, the input pipe is idle. <38>waiting_for_run - waiting for modemanager to complete run setup. <49> running - the pipe is active. <50> waiting_for_pause - the host has issued a pause command. the hostinterfacemanager is waiting for the modemanager to signal pause processing complete. <64> flashgun - grabbing a single frame. <80> stopped - low power 1. can be accessed in all stable states table 11. run mode control index runmodecontrol (1) 0x0280 fmeteringon default value: <1> true purpose if metering is off the auto exposure (ae) and auto white balance (awb) tasks are disabled ty p e flag_e possible values <0> false <1> true 1. can be controlled in all stable states
register map vl6624/VS6624 50/106 mode setup pipe setup bank0 table 12. mode setup index modesetup 0x0302 bnonviewlive_activepipesetupbank (can be controlled in all stable states) default value: <0> pipesetupbank_0 purpose select the active bank for non view live mode ty p e coded possible values <0> pipesetupbank_0 <1>pipesetupbank_1 0x0308 sensormode (must be configured in stop mode) default value <0>sensormode_sxga purpose select the different sensor mode ty p e coded possible values <0>sensormode_sxga <1>sensormode_vga <2>sensormode_vganormal table 13. pipe setup bank0 index pipesetupbank0 (1) 0x0380 bimagesize0 # default value <1> imagesize_sxga purpose required output dimension. ty p e coded possible values <1> imagesize_sxga <2> imagesize_vga <3> imagesize_cif <4> imagesize_qvga <5> imagesize_qcif <6> imagesize_qqvga <7> imagesize_qqcif <8> imagesize_manual - to use manualsubsample and manualcrop controls select manual mode. 0x0383(msb) 0x0384(lsb) uwmanualhsize0 # default value 0x00 purpose if imagesize_manual selected, input required manual h size ty p e uint16
vl6624/VS6624 register map 51/106 0x0387(msb) 0x0388(lsb) uwmanualvsize0 # default value 0x00 purpose if imagesize_manual selected, input required manual v size ty p e uint16 0x038b(msb) 0x038c(lsb) uwzoomstephsize0 default value 0x01 purpose set the zoom h step ty p e uint16 0x038f(msb) 0x0390(lsb) uwzoomstepvsize0 default value 0x01 purpose set the zoom v step ty p e uint16 0x0392 bzoomcontrol0 default value <0> zoomstop purpose control zoom in, zoom out and zoom stop ty p e c possible values <0> zoomstop <1> zoomstart_in <2> zoomstart_out 0x0395(msb) 0x0396(lsb) uwpansteplhsize0 default value 0x00 purpose set the pan h step ty p e uint16 0x0399(msb) 0x039a(lsb) uwpanstepvsize0 default value 0x00 purpose set the panv step ty p e uint16 table 13. pipe setup bank0 index pipesetupbank0 (1)
register map vl6624/VS6624 52/106 0x039c bpancontrol0 default value <0> pan_disable purpose control pandisable, pan right, pan left, pan up, pan down ty p e c possible values <0> pan_disable <1> pan_right <2> pan_left <3> pan_down <4> pan_up 0x039e bcropcontrol0 default value <1> crop_auto purpose select cropping manual or auto ty p e c possible values <0> crop_manual <1> crop_auto 0x03a1(msb) 0x03a2(lsb) uwmanualcrophorizontalstart0 default value 0x00 purpose set the cropping h start address ty p e uint16 0x03a5(msb) 0x03a6(lsb) uwmanualcrophorizontalsize0 default value 0x00 purpose set the cropping h size ty p e uint16 0x03a9(msb) 0x03aa(lsb) uwmanualcropverticalstart0 default value 0x00 purpose set the cropping vstart address ty p e uint16 0x03ad(msb) 0x03ae(lsb) uwmanualcropverticalsize0 default value 0x00 purpose set the cropping vsize ty p e uint16 table 13. pipe setup bank0 index pipesetupbank0 (1)
vl6624/VS6624 register map 53/106 0x03b0 bimageformat0 # (2) default value <0> imageformat_ycbcr_jfif purpose select required output image format. ty p e coded possible values <0> imageformat_ycbcr_jfif <1> imageformat_ycbcr_rec601 <2> imageformat_ycbcr_custom - to use custom output select required rgbtoyuvoutputsignalrange from 'pipesetupbank' page. <3> imageformat_ycbcr_400 <4> imageformat_rgb_565 <5> imageformat_rgb_565_custom - to use custom output select required rgbtoyuvoutputsignalrange from 'pipesetupbank' page. <6> imageformat_rgb_444 <7> imageformat_rgb_444_custom - to use custom output select required rgbtoyuvoutputsignalrange from 'pipesetupbank' page. <9> imageformat_bayer10_throughvp <10> imageformat_bayer8_compthroughvp-- to compress bayer data to 8 bits data <11> imageformat_bayer8_tranthroughvp-- to truncate bayer data to 8 bits data 0x03b2 bbayeroutputalignment0 default value <4> bayeroutputalignment_rightshifted purpose set bayer output alignment ty p e coded possible values <4> bayeroutputalignment_rightshifted <5> bayeroutputalignment_leftshifted 0x03b4 bcontrast0 default value 0x87 purpose contrast control for both ycbcr and rgb output. ty p e byte 0x03b6 bcoloursaturation0 default value 0x78 purpose colour saturation control for both ycbcr and rgb output. ty p e byte 0x03b8 bgamma0 default value 0x0f purpose gamma settings. ty p e byte possible values 0 to 31 table 13. pipe setup bank0 index pipesetupbank0 (1)
register map vl6624/VS6624 54/106 0x03ba fhorizontalmirror0 default value: 0x00 purpose horizontal image orientation flip ty p e flag_e possible values <0> false <1> true 0x03bc fverticalflip0 default value: 0x00 purpose vertical image orientation flip ty p e flag_e possible values <0> false <1> true 0x03be bchanneld default value 0x00 purpose logical dma channel number ty p e byte possible values 0 to 6 1. can be controlled in all stable state. # denotes registers where changes will only be consumed during the transition to a run state. 2. it is possible to switch between any ycrcb (422) mode, rgb mode and bayer 10bit or move between ycrcb 400 and a bayer8 mode without a requiring a transition to stop, it is not possible to move between these groups of modes without first a transition to stop then a boot. table 13. pipe setup bank0 index pipesetupbank0 (1)
vl6624/VS6624 register map 55/106 pipe setup bank1 table 14. pipe setup bank1 index pipesetupbank1 (1) 0x0400 bimagesize1 # default value <1> imagesize_sxga purpose required output dimension. ty p e coded possible values <1> imagesize_sxga <2> imagesize_vga <3> imagesize_cif <4> imagesize_qvga <5> imagesize_qcif <6> imagesize_qqvga <7> imagesize_qqcif <8> imagesize_manual - to use manualsubsample and manualcrop controls select manual mode. 0x0403(msb) 0x0404(lsb) uwmanualhsize1 # default value 0x00 purpose if imagesize_manual selected, input required manual h size ty p e uint16 0x0407(msb) 0x0408(lsb) uwmanualvsize1 # default value 0x00 purpose if imagesize_manual selected, input required manual v size ty p e uint16 0x040b(msb) 0x040c(lsb) uwzoomstephsize1 default value 0x01 purpose set the zoom h step ty p e uint16 0x040f(msb) 0x0410(lsb) uwzoomstepvsize1 default value 0x01 purpose set the zoom v step ty p e uint16
register map vl6624/VS6624 56/106 0x0412 bzoomcontrol1 default value <0> zoomstop purpose control zoom in, zoom out, zoom stop ty p e coded possible values <0> zoomstop <1> zoomstart_in <2> zoomstart_out 0x0415(msb) 0x0416(lsb) uwpansteplhsize1 default value 0x00 purpose set the pan h step ty p e uint16 0x0419(msb) 0x041a(lsb) uwpanstepvsize1 default value 0x00 purpose set the panv step ty p e uint16 0x041c bpancontrol1 default value <0> pan_disable purpose control pandisable, pan right, pan left, pan up, pan down ty p e c possible values <0> pan_disable <1> pan_right <2> pan_left <3> pan_down <4> pan_up 0x041e bcropcontrol1 default value <1> crop_auto purpose select cropping manual or auto ty p e c possible values <0> crop_manual <1> crop_auto 0x0421(msb) 0x0422(lsb) uwmanualcrophorizontalstart1 default value 0x00 purpose set the cropping h start address ty p e uint16 table 14. pipe setup bank1 index pipesetupbank1 (1)
vl6624/VS6624 register map 57/106 0x0425(msb) 0x0426(lsb) uwmanualcrophorizontalsize1 default value 0x00 purpose set the cropping h size ty p e uint16 0x0429(msb) 0x042a(lsb) uwmanualcropverticalstart1 default value 0x00 purpose set the cropping vstart address ty p e uint16 0x042d(msb) 0x042e(lsb) uwmanualcropverticalsize1 default value 0x00 purpose set the cropping vsize ty p e uint16 0x0430 bimageformat1 (2) default value <0> imageformat_ycbcr_jfif purpose select required output image format. ty p e coded possible values <0> imageformat_ycbcr_jfif <1> imageformat_ycbcr_rec601 <2> imageformat_ycbcr_custom - to use custom output select required rgbtoyuvoutputsignalrange from 'pipesetupbank' page. <3> imageformat_ycbcr_400 <4> imageformat_rgb_565 <5> imageformat_rgb_565_custom - to use custom output select required rgbtoyuvoutputsignalrange from 'pipesetupbank' page. <6> imageformat_rgb_444 <7> imageformat_rgb_444_custom - to use custom output select required rgbtoyuvoutputsignalrange from 'pipesetupbank' page. <9> imageformat_bayer10throughvp <10> imageformat_bayer8compthroughvp-- to compress bayer data to 8 bits data <11> imageformat_bayer8tranthroughvp-- to truncate bayer data to 8 bits data 0x0432 bbayeroutputalignment1 default value <4> bayeroutputalignment_rightshifted purpose set bayer output alignment ty p e coded possible values <4> bayeroutputalignment_rightshifted <5> bayeroutputalignment_leftshifted table 14. pipe setup bank1 index pipesetupbank1 (1)
register map vl6624/VS6624 58/106 0x0434 bcontrast1 default value 0x87 purpose contrast control for both ycbcr and rgb output. ty p e byte 0x0436 bcoloursaturation1 default value 0x78 purpose colour saturation control for both ycbcr and rgb output. ty p e byte 0x0438 bgamma1 default value 0x0f purpose gamma settings. ty p e byte possible values 0 to 31 0x043a fhorizontalmirror1 default value 0x00 purpose horizontal image orientation flip ty p e flag_e possible values <0> false <1> true 0x043c fverticalflip1 default value 0x00 purpose vertical image orientation flip ty p e flag_e possible values <0> false <1> true 0x043e bchanneld default value 0x00 purpose logical dma channel number ty p e byte possible values 0 to 6 1. can be controlled in all stable state. # denotes registers where changes will only be consumed during the transition to a run state. 2. it is possible to switch between any ycrcb (422) mode, rgb mode and bayer 10bit or move between ycrcb 400 and a bayer8 mode without a requiring a transition to stop, it is not possible to move between these groups of modes without first a transition to stop then a boot. table 14. pipe setup bank1 index pipesetupbank1 (1)
vl6624/VS6624 register map 59/106 viewlive control viewlive status [read only] table 15. viewlive control index viewlivecontrol 0x0480 fenable (can be controlled in all stable states) default value <0> false purpose set to enable the view live mode. ty p e flag_e possible values <0> false <1> true 0x0482 binitialpipesetupbank (must be setup in pause or stop mode) default value <0> pipesetupbank_0 purpose first frame output will be from pipesetupbank selected by 'binitialpipesetupbank'. if viewlive is enabled the next frame will be from the other pipesetupbank, otherwise only one pipesetupbank will be used. ty p e coded possible values <0> pipesetupbank_0 <1> pipesetupbank_1 table 16. viewlive status index viewlivestatus [read only] 0x0500 currentpipesetupbank default value <0> pipesetupbank_0 purpose indicates the pipesetupbank which has most recently been applied to the pixel pipe hardware. ty p e coded possible values <0> pipesetupbank_0 <1> pipesetupbank_1
register map vl6624/VS6624 60/106 power management video timing parameter host inputs video timing control table 17. power management index powermanagement (1) 0x0580 btimetopowerdown default value 0x0f purpose time (msecs) from entering pause mode until the system automatically transitions stop mode. 0xff disables the automatic transition. ty p e byte 1. must be configured in stop mode table 18. video timing parameter host inputs index videotimingparameterhostinputs (1) 0x0605 (msbyte) 0x0606 (lsbyte) uwexternalclockfrequencymhznumerator default value 0x0c purpose specifies the external clock frequency... external clock frequency = uwexternalclockfrequencymhznumerator/bexternalclockfrequencymh zdenominator ty p e uint16 0x0608 bexternalclockfrequencymhzdenominator default value 0x01 ty p e byte 1. should be configured in the raw state table 19. video timing control index videotimingcontrol (1) 0x0880 bsysclkmode default value 0x00 purpose decides system centre clock frequency ty p e coded possible values <0>12mhz mode <1>13mhz mode <2>13.5mhz mode <3>slave mode 1. should be configured in the raw state
vl6624/VS6624 register map 61/106 frame dimension parameter host inputs static frame rate control table 20. frame dimension parameter host inputs index framedimensionparameterhostinputs (1) 0x0c80 blightingfrequencyhz default value 0x00 purpose ac frequency - used for flicker free time period calculations this mains frequency determines the flicker free time period. ty p e byte 0x0c82 fflickercompatibleframelength default value <0> false purpose flicker_compatible_frame_length ty p e flag_e possible values <0> false <1> true 1. can be controlled in all stable states table 21. static frame rate control index staticframeratecontrol (1) 0x0d81 (msbyte) 0x0d82 (lsbyte) uwdesiredframerate_num default value 0x0f purpose numerator for the frame rate ty p e uint16 0x0d84 bdesiredframerate_den default value 0x01 purpose denominator for the frame rate ty p e byte 1. can be controlled in all stable states
register map vl6624/VS6624 62/106 automatic frame rate control exposure controls table 22. automatic frame rate control index automaticframeratecontrol (1) 0x0e80 bdisableframeratedamper default value 0x00 purpose defines the mode in which the framerate of the system would work ty p e possible values <0> manual <1> auto 0x0e8c (msbyte) 0x0e8a (lsbyte) bminimumdamperoutput default value 0x00 purpose sets the minimum framerate employed when in automatic framerate mode. ty p e uint16 1. can be controlled in all stable states table 23. exposure controls index exposurecontrols (1) 0x1180 bmode default value <0> automatic_mode purpose sets the mode for the exposure algorithm ty p e coded possible values <0> automatic_mode - automatic mode of exposure which includes computation of relative step <1> compiled_manual_mode - compiled manual mode in which the desired exposure is given and not calculated by algorithm <2> direct_manual_mode - mode in which the exposure parameters are input directly and not calculated by compiler <3> flashgun_mode - flash gun mode in which the exposure parameters are set to fixed values
vl6624/VS6624 register map 63/106 0x1182 bmetering default value <0> exposuremetering_flat purpose weights to be associated with the zones for calculating the mean statistics exposure weight could centered, backlit or flat ty p e c possible values <0> exposuremetering_flat - uniform gain associated with all pixels <1> exposuremetering_backlit - more gain associated with centre pixels and bottom pixels <2> exposuremetering_centred - more gain associated with centre pixels 0x1184 bmanualexposuretime_num default value 0x01 purpose exposure time for compiled manual mode in seconds. num/den gives required exposure time ty p e byte 0x1186 bmanualexposuretime_den default value 0x1e ty p e byte 0x1189 (msbyte) 0x118a (lsbyte) fpmanualfloatexposuretime default value 0x59aa (15008) purpose exposure time for the manual mode. this value is in usecs ty p e float 0x1190 iexposurecompensation default value 0x00 purpose exposure compensation - a user choice for setting the runtime target. a unit of exposure compensation corresponds to 1/6 ev. default value according to the nominal target of 30 is 0. coded value of exposure compensation can take values from -25 to 12. ty p e int8 0x1195 (msbyte) 0x1196 (lsbyte) uwdirectmodecoarseintegrationlines default value 0x00 purpose coarse integration lines to be set for direct mode ty p e uint16 table 23. exposure controls index exposurecontrols (1)
register map vl6624/VS6624 64/106 0x1199 (msbyte) 0x119a (lsbyte) uwdirectmodefineintegrationpixels default value 0x00 purpose fine integration pixels to be set for direct mode ty p e uint16 0x119d (msbyte) 0x119e (lsbyte) fpdirectmodeanaloggain default value 0x00 purpose analog gain to be set for direct mode ty p e float 0x11a1 (msbyte) 0x11a2 (lsbyte) fpdirectmodedigitalgain default value 0x00 purpose digital gain to be set for direct mode ty p e float 0x11a5 (msbyte) 0x11a6 (lsbyte) uwflashgunmodecoarseintlines default value 0x00 purpose coarse integration lines to be set for flash gun mode ty p e uint16 0x11a9 (msbyte) 0x11aa (lsbyte) uwflashgunmodefineintpixels default value 0x00 purpose fine integration pixels to be set for flash gun mode ty p e uint16 0x11ad (msbyte) 0x11ae (lsbyte) fpflashgunmodeanaloggain default value 0x00 purpose analog gain to be set for flash gun mode ty p e float 0x11b1 (msbyte) 0x11b2 (lsbyte) fpflashgunmodedigitalgain default value 0x00 purpose digital gain to be set for flash gun mode ty p e float table 23. exposure controls index exposurecontrols (1)
vl6624/VS6624 register map 65/106 0x11b4 ffreezeautoexposure default value <0> false purpose freeze auto exposure ty p e flag_e possible values <0> false <1> true 0x11b7 (msbyte) 0x11b8 (lsbyte) fpusermaximumintegrationtime default value 0x647f (654336) purpose user maximum integration time in microseconds. this control takes in the maximum integration time that host would like to support. this would in turn give an idea of the degree of ?wobbly pencil effect? acceptable to host. ty p e float 0x11bb (msbyte) 0x11bc (lsbyte) fprecommendflashgunanaloggainthreshold default value 0x4200 (4) purpose recommend flash gun analog gain threshold value ty p e float 0x11c0 bantiflickermode default value <0> antiflickermode_inhibit purpose anti flicker mode ty p e coded possible values <0> antiflickermode_inhibit <1> antiflickermode_manualenable <2>antiflickermode_automaticenable 1. can be controlled in all stable states table 23. exposure controls index exposurecontrols (1)
register map vl6624/VS6624 66/106 white balance control table 24. white balance control parameters index wbcontrolparameters (1) 0x1480 bmode default value <1> automatic purpose for setting mode of the white balance ty p e coded possible values <0> off - no white balance, all gains will be unity in this mode <1> automatic - automatic mode, relative step is computed here <3> manual_rgb - user manual mode, gains are applied manually <4> daylight_preset - daylight and all the modes below, fixed value of gains are applied here. <5> tungsten_preset <6> fluorescent_preset <7> horizon_preset <8> manual_colour_temp <9> flashgun_preset 0x1482 bmanualredgain default value 0x00 purpose user setting for red channel gain ty p e byte 0x1484 bmanualgreengain default value 0x00 purpose user setting for green channel gain ty p e byte 0x1486 bmanualbluegain default value 0x00 purpose user setting for blue channel gain ty p e byte 0x148b (msbyte) 0x148c (lsbyte) fpflashredgain default value 0x3e80 (1.250) purpose redgain for flashgun ty p e float 0x148f (msbyte) 0x1490 (lsbyte) fpflashgreengain default value 0x3e00 (1.000) purpose green gain for flashgun ty p e float
vl6624/VS6624 register map 67/106 sensor setup image stability [read only] 0x1493 (msbyte) 0x1494 (lsbyte) fpflashbluegain default value 0x3e8a (1.269531) purpose bluegain for flashgun ty p e float 1. can be controlled in all stable states table 24. white balance control parameters index wbcontrolparameters (1) table 25. sensor setup index sensorsetup (1) 0x1990 bblackcorrectionoffset default value 0x00 purpose black correction offset which would be added to the sensor pedestal to get the re offset. this is to improve the black level. ty p e byte 1. can be controlled in all stable states table 26. image stability [read only] index image stability [read only] 0x1900 fwhitebalancestable default value 0x00 purpose specifies that white balance system is stable/unstable ty p e coded possible values <0> unstable <1>stable 0x1902 fexposurestable default value 0x00 purpose specifies that white balance system is stable/unstable ty p e coded possible values <0> unstable <1>stable
register map vl6624/VS6624 68/106 flash control 0x1906 fstable default value 0x00 purpose consolidated flag to indicate whether the system is stable/unstable ty p e coded possible values <0> unstable <1>stable table 26. image stability [read only] index image stability [read only] table 27. flash control index flashcontrol (1) 0x1a80 bflashmode default value <0> flash_off purpose select the flash type and on/off ty p e coded possible values <0> flash_off <1>flash_torch <2>flash_pulse 0x1a83(msb) 0x1a84(lsb) uwflashoffline default value 0x021c (540) purpose at flash_pulse mode, used to control off line ty p e uint16 1. can be controlled in all stable states
vl6624/VS6624 register map 69/106 flash status [read only] scythe filter controls jack filter controls table 28. flash status index flashstatus [read only] 0x1b00 fflashrecommend default value <0> false purpose this flag is set if the exposure control system reports that the image is underexposed and so the flashgun is recommended to the host. it is at the discretion of host to use it or not for the following still grab. ty p e flag_e possible values <0> false <1> true 0x1b02 fflashgrabcomplete default value <0> false purpose this flag indicates that the flashgun image has been grabbed. ty p e flag_e possible values <0> false <1> true table 29. scythe filter controls index scythefiltercontrols (1) 0x1d80 fdisablefilter default value <0> false purpose disable scythe defect correction ty p e flag_e possible values <0> false <1> true 1. can be controlled in all stable state table 30. jack filter controls index jackfiltercontrols (1) 0x1e00 fdisablefilter default value <0> false purpose disable jack defect correction ty p e flag_e possible values <0> false <1> true 1. can be controlled in all stable state
register map vl6624/VS6624 70/106 demosaic control colour matrix dampers table 31. demosaic control index demosaiccontrol (1) 0x1e80 bantialiasfiltersuppress default value 0x08 purpose anti alias filter suppress ty p e byte 1. can be controlled in all stable state table 32. colour matrix dampers index colourmatrixdamper (1) 0x1f00 fdisable default value <0> false purpose set to disable colour matrix damper and therefore ensure that all the colour matrix coefficients remain constant under all conditions. ty p e flag_e possible values <0> false <1> true 0x1f03 (msbyte) 0x1f04 (lsbyte) fplowthreshold default value 0x67d1 (2000896) purpose low threshold for exposure for calculating the damper slope ty p e float 0x1f07 (msbyte) 0x1f08 (lsbyte) fphighthreshold default value 0x6862 (2498560) purpose high threshold for exposure for calculating the damper slope ty p e float 0x1f0b (msbyte) 0x1f0c (lsbyte) fpminimumoutput default value 0x3acd (0.350098) purpose minimum possible damper output for the colourmatrix ty p e float 1. can be controlled in all stable state
vl6624/VS6624 register map 71/106 peaking control table 33. peaking control index peaking control (1) 0x2000 buserpeakgain default value 0x0e purpose controls peaking gain / sharpness applied to the image ty p e byte 0x2002 fdisablegaindamping default value <0> false purpose set to disable damping and therefore ensure that the peaking gain applied remains constant under all conditions ty p e flag_e possible values <0> false <1> true 0x2005 (msbyte) 0x2006 (lsbyte) fpdamperlowthreshold_gain default value 0x62ac (350208) purpose low threshold for exposure for calculating the damper slope - for gain ty p e float 0x2009 (msbyte) 0x200a (lsbyte) fpdamperhighthreshold_gain default value 0x65d1 (10004488) purpose high threshold for exposure for calculating the damper slope - for gain ty p e float 0x200d (msbyte) 0x200e (lsbyte) fpminimumdamperoutput_gain default value 0x3d33 (0.799805) purpose minimum possible damper output for the gain. ty p e float 0x2010 buserpeaklothresh default value 0x1e purpose adjust degree of coring. range: 0 - 63 ty p e byte 0x2012 fdisablecoringdamping default value <0> false purpose set to ensure that buserpeaklothresh is applied to gain block ty p e flag_e possible values <0> false <1> true
register map vl6624/VS6624 72/106 0x2014 buserpeakhithresh default value 0x30 purpose adjust maximum gain that can be applied. range: 0 - 63 ty p e byte 0x2017 (msbyte) 0x2018 (lsbyte) fpdamperlowthreshold_coring default value 0x624a (300032) purpose low threshold for exposure for calculating the damper slope - for coring ty p e float 0x201b (msbyte) 0x201c (lsbyte) fpdamperhighthreshold_coring default value 0x656f (900096) purpose high threshold for exposure for calculating the damper slope - for coring ty p e float 0x201f (msbyte) 0x2020 (lsbyte) fpminimumdamperoutput_coring default value 0x3a00 (0.2500) purpose minimum possible damper output for the coring. ty p e float 1. can be controlled in all stable states table 33. peaking control index peaking control (1)
vl6624/VS6624 register map 73/106 pipe 0 rgb to yuv matrix manual control table 34. pipe0 rgb to yuv matrix manual control index pipe0rgb to yuv matrix (1) 0x2180 frgbtoyuvmanuctrl default value <0> false purpose enables manual rgb to yuv matrix for pipesetupbank0 ty p e flag_e possible values <0> false <1> true 0x2183 (msbyte) 0x2184(lsbyte) w0_0 default value 0x00 purpose row 0 column 0 of yuv matrix ty p e uint_16 0x2187 (msbyte) 0x2188 (lsbyte) w0_1 default value 0x00 purpose row 0 column 1 of yuv matrix ty p e uint_16 0x218c (msbyte) 0x218d (lsbyte) w0_2 default value 0x00 purpose row 0 column 2 of yuv matrix ty p e uint_16 0x2190 (msbyte) 0x218f (lsbyte) w1_0 default value 0x00 purpose row 1 column 0 of yuv matrix ty p e uint_16 0x2193 (msbyte) 0x2194 (lsbyte) w1_1 default value 0x00 purpose row 1 column 1 of yuv matrix ty p e uint_16 0x2197 (msbyte) 0x2198 (lsbyte) w1_2 default value 0x00 purpose row 1 column 2 of yuv matrix ty p e uint_16
register map vl6624/VS6624 74/106 0x219b (msbyte) 0x219c (lsbyte) w2_0 default value 0x00 purpose row 2 column 0 of yuv matrix ty p e uint_16 0x21a0 (msbyte) 0x219f (lsbyte) w2_1 default value 0x00 purpose row 2 column 1 of yuv matrix ty p e uint_16 0x21a3 (msbyte) 0x21a4 (lsbyte) w2_2 default value 0x00 purpose row 2 column 2 of yuv matrix ty p e uint_16 0x21a7 (msbyte) 0x21a8 (lsbyte) yiny default value 0x00 purpose y in y ty p e uint_16 0x21ab (msbyte) 0x21ac (lsbyte) yincb default value 0x00 purpose y in cb ty p e uint_16 0x21b0 (msbyte) 0x21af (lsbyte) yincr default value 0x00 purpose y in cr ty p e uint_16 1. can be controlled in all stable states table 34. pipe0 rgb to yuv matrix manual control index pipe0rgb to yuv matrix (1)
vl6624/VS6624 register map 75/106 pipe 1 rgb to yuv matrix manual control table 35. pipe1 rgb to yuv matrix manual control index pipe1rgbtoyuv (1) 0x2200 frgbtoyuvmanuctrl default value <0> false purpose enables manual rgb to yuv matrix for pipesetupbank1 ty p e flag_e possible values <0> false <1> true 0x2203 (msbyte) 0x2204(lsbyte) w0_0 default value 0x00 purpose row 0 column 0 of yuv matrix ty p e uint_16 0x2207 (msbyte) 0x2208 (lsbyte) w0_1 default value 0x00 purpose row 0 column 1 of yuv matrix ty p e uint_16 0x220c (msbyte) 0x220d (lsbyte) w0_2 default value 0x00 purpose row 0 column 2 of yuv matrix ty p e uint_16 0x2210 (msbyte) 0x220f (lsbyte) w1_0 default value 0x00 purpose row 1 column 0 of yuv matrix ty p e uint_16 0x2213 (msbyte) 0x2214 (lsbyte) w1_1 default value 0x00 purpose row 1 column 1 of yuv matrix ty p e uint_16 0x2217 (msbyte) 0x2218 (lsbyte) w1_2 default value 0x00 purpose row 1 column 2 of yuv matrix ty p e uint_16
register map vl6624/VS6624 76/106 0x221b (msbyte) 0x221c (lsbyte) w2_0 default value 0x00 purpose row 2 column 0 of yuv matrix ty p e uint_16 0x2220 (msbyte) 0x221f (lsbyte) w2_1 default value 0x00 purpose row 2 column 1 of yuv matrix ty p e uint_16 0x2223 (msbyte) 0x2224 (lsbyte) w2_2 default value 0x00 purpose row 2 column 2 of yuv matrix ty p e uint_16 0x2227 (msbyte) 0x2228 (lsbyte) yiny default value 0x00 purpose y in y ty p e uint_16 0x222b (msbyte) 0x222c (lsbyte) yincb default value 0x00 purpose y in cb ty p e uint_16 0x2220 (msbyte) 0x222f (lsbyte) yincr default value 0x00 purpose y in cr ty p e uint_16 1. can be controlled in all stable states table 35. pipe1 rgb to yuv matrix manual control index pipe1rgbtoyuv (1)
vl6624/VS6624 register map 77/106 pipe 0 gamma manual control table 36. pipe 0 gamma manual control index pipe0 gammamanucontrol (1) 0x2280 fgammamanuctrl default value <0> false purpose enables manual gamma setup for pipesetupbank0 ty p e flag_e possible values <0> false <1> true 0x2282 brpeakgamma default value 0x00 purpose peaked red channel gamma value ty p e byte 0x2284 bgpeakgamma default value 0x00 purpose peaked green channel gamma value ty p e byte 0x2286 bbpeakgamma default value 0x00 purpose peaked blue channel gamma value ty p e byte 0x2288 brunpeakgamma default value 0x00 purpose unpeaked red channel gamma value ty p e byte 0x228a bgunpeakgamma default value 0x00 purpose unpeaked green channel gamma value ty p e byte 0x228c bbunpeakgamma default value 0x00 purpose unpeaked blue channel gamma value ty p e byte 1. can be controlled in all stable states
register map vl6624/VS6624 78/106 pipe 1 gamma manual control table 37. pipe 1 gamma manual control index pipe1gammamanucontrol (1) 0x2300 fgammamanuctrl default value <0> false purpose enables manual gamma setup for pipesetupbank1 ty p e flag_e possible values <0> false <1> true 0x2302 brpeakgamma default value 0x00 purpose peaked red channel gamma value ty p e byte 0x2304 bgpeakgamma default value 0x00 purpose peaked green channel gamma value ty p e byte 0x2306 bbpeakgamma default value 0x00 purpose peaked blue channel gamma value ty p e byte 0x2308 brunpeakgamma default value 0x00 purpose unpeaked red channel gamma value ty p e byte 0x230a bgunpeakgamma default value 0x00 purpose unpeaked green channel gamma value ty p e byte 0x230c bbunpeakgamma default value 0x00 purpose unpeaked blue channel gamma value ty p e byte 1. can be controlled in all stable states
vl6624/VS6624 register map 79/106 fade to black table 38. fade to black index fadetoblack (1) 0x2480 fdisable default value <0> false purpose flag_e ty p e <0> false <1> true 0x2483 (msbyte) 0x2484(lsbyte) fpblackvalue default value 0x0000 (0.000) purpose black value ty p e float 0x2487 (msbyte) 0x2488 (lsbyte) fpdamperlowthreshold default value 0x6d56 (6995968) purpose low threshold for exposure for calculating the damper slope ty p e float 0x248b (msbyte) 0x248c (lsbyte) fpdamperhighthreshold default value 0x6cdc (11993088) purpose high threshold for exposure for calculating the damper slope ty p e float 0x248f (msbyte) 0x2490 (lsbyte) fpdamperoutput default value 0x0 (0.0000) purpose minimum possible damper output. ty p e float 1. can be controlled in all stable states
register map vl6624/VS6624 80/106 output formatter control table 39. output formatter control index outputformattercontrol (1) 0x2580 bcodechecken default value 0x07 ty p e byte 0x2582 bblankformat default value 0x00 ty p e byte 0x2584 bsynccodesetup default value 0x01 ty p e coded flag bits [0] synccodesetup_ins_code_en - set for embedded sync codes. [1] synccodesetup_frame_mode - 0 for itu. 1 for mode2 [2] synccodesetup_field_bit [3] synccodesetup_field_tag [4] synccodesetup_field_load 0x2586 bhsyncsetup default value 0x0b ty p e coded flag bits [0] hsyncsetup_sync_en [1] hsyncsetup_sync_pol [2] hsyncsetup_only_activelines [3] hsyncsetup_track_henv 0x2588 bvsyncsetup default value 0x07 ty p e coded flag bits [0] vsyncsetup_sync_en [1] vsyncsetup_pol [2] vsyncsetup_2_sel
vl6624/VS6624 register map 81/106 0x258a bpclksetup default value 0x05 ty p e coded flag bits [0] pclksetup_prog_lo [1] pclksetup_prog_hi [2] pclksetup_sync_en [3] pclksetup_hsync_en_n [4] pclksetup_hsync_en_n_track_internal [5] pclksetup_vsync_n [6] pclksetup_vsync_n_track_internal [7] pclksetup_freer 0x258c fpclken default value <1> true ty p e flag_e possible values <0> false <1> true 0x258e bopfspsetup default value 0x00 type byte 0x2590 bblankdata_msb default value 0x10 ty p e coded possible values <16> blankingmsb_default 0x2592 bblankdata_lsb default value 0x80 ty p e coded possible values <128> blankinglsb_default 0x2594 brgbsetup default value 0x00 ty p e coded flag bits [0] rgbsetup_rgb444_itu_zp [1] rgbsetup_rb_swap [2] rgbsetup_bit_reverse [3] rgbsetup_softreset table 39. output formatter control index outputformattercontrol (1)
register map vl6624/VS6624 82/106 0x2596 byuvsetup default value 0x00 ty p e coded flag bits [0] yuvsetup_u_first [1] yuvsetup_y_first 0x2598 bvsyncrisingcoarseh default value 0x00 ty p e byte 0x259a bvsyncrisingcoarsel default value 0x00 ty p e byte 0x259c bvsyncrisingfineh default value 0x00 ty p e byte 0x259e bvsyncrisingfinel default value 0x01 ty p e byte 0x25a0 bvsyncfallingcoarseh default value 0x01 ty p e byte 0x25a2 bvsyncfallingcoarsel default value 0xf2 ty p e byte 0x25a4 bvsyncfallingfineh default value 0x00 ty p e byte 0x25a6 bvsyncfallingfinel default value 0x01 ty p e byte 0x25a8 bhsyncrisingh default value 0x00 ty p e byte table 39. output formatter control index outputformattercontrol (1)
vl6624/VS6624 register map 83/106 0x25aa bhsyncrisingl default value 0x03 ty p e byte 0x25ac bhsyncfallingh default value 0x00 ty p e byte 0x25ae bhsyncfallingl default value 0x07 type byte 0x25b0 boutputinterface default value [0] outputinterface_itu ty p e coded flag bits [0] outputinterface_itu [1] outputinterface_ccp_datastrobe [2] outputinterface_ccp_dataclock 0x25b2 bccpextradata default value 0x08 ty p e byte 1. can be controlled in all stable states table 39. output formatter control index outputformattercontrol (1)
register map vl6624/VS6624 84/106 nora controls table 40. nora controls index noracontrols (1) 0x2600 fdisable default value <0> noractrl_auto ty p e flag_e possible values <0> noractrl_auto - switches off nora for scaled outputs <1> noractrl_manudisable - always off <2> noractrl_manuenable - always on 0x2602 busage default value 0x04 purpose ty p e byte 0x2604 bsplit_kn default value 0x01 purpose ty p e byte 0x2606 bsplit_nl default value 0x01 purpose ty p e byte 0x2608 btight_green default value 0x01 purpose ty p e byte 0x260a fdisablenoropromoting default value <0> false ty p e flag_e possible values <0> false <1> true 0x260d (msbyte) 0x260e (lsbyte) fpdamperlowthreshold default value 0x6862 (2498560) purpose low threshold for exposure for calculating the damper slope ty p e float
vl6624/VS6624 register map 85/106 0x2611 (msbyte) 0x2612 (lsbyte) fpdamperhighthreshold default value 0x6a62 (4997120) purpose high threshold for exposure for calculating the damper slope ty p e float 0x2615 (msbyte) 0x2616 (lsbyte) minimumdamperoutput default value 0x3a00 (0.2500) purpose minimum possible damper output. ty p e float 1. can be controlled in all stable states table 40. nora controls index noracontrols (1)
optical specifications vl6624/VS6624 86/106 12 optical specifications 12.1 average sensitivity the average sensitivity is a measure of the image sensor response to a given light stimulus. the optical stimulus is a white light source with a color temperature of 3200k, producing uniform illumination at the surface of the sensor package. an ir blocking filter is added to the light source. the analog gain of the sensor is set to x1. the exposure time, t, is set as 50% of maximum. the illuminance, i, is adjusted so the average sensor output code, xlight, is roughly mid-range equivalent to a saturation level of 50%. once xlight has been recorded the experiment is repeated with no illumination to give a value xdark. the sensitivity is then calculated as .the result is expressed in volts per lux- second. the sensitivity of the VS6624 is given in ta bl e 4 2 . table 41. optical specifications (1) 1. all measurements made at 23c 2c parameter min. typ. max. unit optical format 1/3 inch effective focal length mm aperture (f number) 3.2 horizontal field of view 52 deg. depth of field 60 infinity cm tv distortion 1 % table 42. VS6624 average sensitivity optical parameter VS6624 unit average sensitivity 0.49 v/lux.s xlight xdark ? tl ? ---------------------------------------
vl6624/VS6624 optical specifications 87/106 12.2 spectral response the spectral response for the vs6524 sensor is shown in figure 32 figure 32. quantum efficiency (h8s1 - 3.0 m pixel
electrical characteristics vl6624/VS6624 88/106 13 electrical characteristics 13.1 absolute maximum ratings caution: stress above those listed under ?absolute maximum ratings? can cause permanent damage to the device. this is a stress rating only and functional operations of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 13.2 operating conditions table 43. absolute maximum ratings symbol parameter min. max. unit t sto storage temperature -40 85 c v dd digital power supplies -0.5 3.3 v avdd analog power supplies -0.5 3.3 v table 44. supply specifications symbol parameter min. typ. max. unit t af operating temperature, functional (camera is electrically functional) -30 25 70 c t an operating temperature, nominal (camera produces acceptable images) -25 25 55 c t ao operating temperature, optimal (camera produces optimal optical performance) 52530c v dd digital power supplies operating range (@ module pin (1) ) 1. module can contain routing resistance up to 5 . 1.7 1.8 2.0 v 2.4 2.8 3.0 v avdd analog power supplies operating range (@ module pin (1) ) 2.4 2.8 3.0 v
vl6624/VS6624 electrical characteristics 89/106 13.3 dc electrical characteristics note: over operating conditions unless otherwise specified. table 45. dc electrical characteristics symbol description test conditions min. typ. max. unit v il input low voltage vdd 1.7~ 2.0v -0.3 0.25 v dd v vdd 2.4 ~ 3.0v -0.3 0.3 v dd v v ih input high voltage 0.7 v dd v dd + 0.3 v v ol output low voltage i ol < 2 ma i ol < 4 ma 0.2 v dd 0.4 v dd v v oh output high voltage i oh < 4 ma 0.8 v dd v i il input leakage current input pins i/o pins 0 < v in < v dd +/- 10 +/- 1 a a c in input capacitance, scl t a = 25 c, freq = 1 mhz 6 pf c out output capacitance t a = 25 c, freq = 1 mhz 6 pf c i/o i/o capacitance, sda t a = 25 c, freq = 1 mhz 8 pf table 46. typical current consumption - sensor mode vga 30 fps symbol description test conditions i avdd i vdd units v dd = 2.8v v dd = 1.8v v dd = 2.8v i pd supply current in power down mode ce=0, clk = 12 mhz 1.4 0.05 0.07 a i stanby supply current in standby mode ce=1, clk = 12 mhz 0.0014 1.3 8 ma i stop supply current in stop mode ce=1, clk = 12 mhz 0.0014 4.1 4.2 ma i pause supply current in pause mode ce=1, clk = 12 mhz 0.00175 43.8 43.3 ma i run supply current in active streaming run mode ce=1, clk = 12 mhz streaming vga @30 fps 11.3 55.1 54.8 ma
electrical characteristics vl6624/VS6624 90/106 13.4 external clock the vl6624/VS6624 requires an external clock. this clock is a cmos digital input. the clock input is fail-safe in power down mode. 13.5 chip enable ce is a cmos digital input. the module is powered down when a logic 0 is applied to ce. see power up sequence for further information. table 47. typical current consumption - sensor mode sxga 15 fps symbol description test conditions i avdd i vdd units v dd = 2.8v v dd = 1.8v v dd = 2.8v i pd supply current in power down mode ce=0, clk = 12 mhz 1.4 0.05 0.07 a i stanby supply current in standby mode ce=1, clk = 12 mhz 0.0014 1.3 8 ma i stop supply current in stop mode ce=1, clk = 12 mhz 0.0014 4.1 4 ma i pause supply current in pause mode ce=1, clk = 12 mhz 0.0195 63.4 64.7 ma i run supply current in active streaming run mode ce=1, clk = 12 mhz streaming vga @30 fps 11.5 84.5 87 ma table 48. external clock clk range unit min. typ. max. dc coupled square wave vdd v clock frequency (normal operation) 6.50 6.50, 8.40, 9.60, 9.72, 12.00, 13.00, 16.80, 19.20, 19.44 54 mhz
vl6624/VS6624 electrical characteristics 91/106 13.6 i2c slave interface vl6624/VS6624 contains an i2c-type interface using two signals: a bidirectional serial data line (sda) and an input-only serial clock line (scl). see host communication - i2c control interface for detailed description of protocol. figure 33. voltage level specification table 49. serial interface voltage levels (1) symbol parameter standard mode fast mode unit min. max. min. max. v hys hysteresis of schmitt trigger inputs v dd > 2 v v dd < 2v n/a n/a n/a n/a 0.05 v dd 0.1 v dd - - v v v ol1 v ol3 low level output voltage (open drain) at 3ma sink current v dd > 2 v v dd < 2v 0 n/a 0.4 n/a 0 0 0.4 0.2 v dd v v v oh high level output voltage n/a n/a 0.8 v dd v t of output fall time from v ihmin to v ilmax with a bus capacitance from 10 pf to 400 pf - 250 20+0.1c b (2) 250 ns t sp pulse width of spikes which must be suppressed by the input filter n/a n/a 0 50 ns 1. maximum v ih = v ddmax + 0.5 v 2. c b = capacitance of one bus line in pf v oh v ol input voltage levels output voltage levels v il v ih
electrical characteristics vl6624/VS6624 92/106 table 50. timing specification (1) symbol parameter standard mode fast mode unit min. max. min. max. f scl scl clock frequency 0 100 0 400 khz t hd;sta hold time for a repeated start 4.0 - 0.6 - s t low low period of scl 4.7 - 1.3 - s t high high period of scl 4.0 - 0.6 - s t su;sta set-up time for a repeated start 4.7 - 0.6 - s t hd;dat data hold time (1) 300 - 300 - ns t su;dat data set-up time (1) 250 - 100 - ns t r rise time of scl, sda - 1000 20+0.1c b (2) 300 ns t f fall time of scl, sda - 300 20+0.1c b (2) 300 ns t su;sto set-up time for a stop 4.0 - 0.6 - s t buf bus free time between a stop and a start 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf v nl noise margin at the low level for each connected device (including hysteresis) 0.1 v dd - 0.1 v dd - v v nh noise margin at the high level for each connected device (including hysteresis) 0.2 v dd - 0.2 v dd - v 1. all values are referred to a v ihmin = 0.9 v dd and v ilmax = 0.1 v dd 2. c b = capacitance of one bus line in pf
vl6624/VS6624 electrical characteristics 93/106 figure 34. timing specification figure 35. sda/scl rise and fall times all values are referred to a v ihmin = 0.9 v dd and v ilmax = 0.1 v dd sda scl start stop start t buf t low t high t hd;sta t hd;dat t su;dat t su;sta t su;sto t hd;sta t f t r t sp s ps 0.9 * v dd 0.1 * v dd 0.9 * v dd 0.1 * v dd t f t r
electrical characteristics vl6624/VS6624 94/106 13.7 parallel data interface timing vl6624/VS6624 contains a parallel data output port (d[7:0]) and associated qualification signals (hsync, vsync, pclk and fso). this port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or bit-serial output configurations. the port is disabled (high impedance) upon reset. figure 36. parallel data output video timing table 51. parallel data interface timings symbol description min. max. unit f pclk pclk frequency 54 mhz t pclkl pclk low width [1/2*(1/f pclk )] - 3.9 [1/2*(1/f pclk )] + 3.9 ns t pclkh pclk high width [1/2*(1/f pclk )] - 3.9 [1/2*(1/f pclk )] + 3.9 ns t dv pclk to output valid -5.15 1.62 ns t pclkl t pclkh 1/f pclk pclk d[0:7] hsync, polarity = 0 t dv valid vsync
vl6624/VS6624 user precaution 95/106 14 user precaution as is common with many cmos imagers the camera should not be pointed at bright static objects for long periods of time as permanent damage to the sensor may occur.
package mechanical data vl6624/VS6624 96/106 15 package mechanical data 15.1 smop figure 37 and figure 38 present the package outline socket module VS6624q0kp. figure 39 and figure 40 present the package outline fpc module VS6624p0lp.
vl6624/VS6624 package mechanical data 97/106 figure 37. package outline socket module VS6624q0kp 7.65 at a r 0 . 1 0 in mm do not scale a b c d e f a b c d e f sheet scale 2 1 3 4 5 6 78 1 3 2 7 6 8 title material finish and will not be copied or loaned without the 0.10 sig. date drawn written permission of stmicroelectronics. position all dimensions in mm part no. interpret drawing per bs308, 3rd angle projection tolerances, unless otherwise stated surface finish 1.6 microns linear 0 place decimals 0 0.10 1 place decimals 0.0 0.07 2 place decimals 0.00 0.05 angular 0.25 degrees diameter +0.10/-0.00 this drawing is the property of stmicroelectronics all dimensions home, personal & communications sector 7.6 a 7.88 c 1 . 5 5 0 . 1 0 0 . 6 3 1 . 1 3 5 r e f 0 . 0 4 1 . 5 7 0 . 0 6 0 . 6 0 c (32 : 1) socket version 7899903 1 of 2 624 camera outline revisions zone rev. description date 1 1st release for comment 31/08/2005 2 sheet 2 added, scallop dimensions changed 01/09/2005 3 sheet: 1.55 was 1.50 sheet 2, pin out info clarified 05/09/2005 4.10 0.10 0.10 6.30 0.03 7.0 4 . 0 8.00 ch, 0.60x45 0.05 ch 0.40x45, 3 posns stmicroelectronics
package mechanical data vl6624/VS6624 98/106 figure 38. package outline socket module VS6624q0kp 0.15 0.03 6 8 5 7 a 2.64 3.52 4.40 pin 1 top of scene 624 camera outline 2 of 2 7899903 0.55 0.00 +0.02 d (32 : 1) 1.00 1.75 2.65 3.55 4.45 5.35 6.25 1.75 2.65 3.55 4.45 5.35 6.25 0.70 1.00 0.50 0.90 1.00 2.30 0.90 0.60 x 45 pin 1 pin 7 pin 18 pin 24 pad layout (partial section) d 4 4 a b c d e f a b c d e f sheet scale 2 1 3 4 5 6 78 1 3 2 7 6 8 title material finish tolerances, unless otherwise stated linear 0 place decimals 0 1.0 1 place decimals 0.0 0.10 2 place decimals 0.00 0.07 angular 0.25 degrees diameter +0.10/-0.00 position 0.10 surface finish 1.6 microns interpret drawing per bs308, 3rd angle projection all dimensions in mm this drawing is the property of stmicroelectronics and will not be copied or loaned without the written permission of stmicroelectronics. drawn sig. date part no. all dimensions in mm do not scale home, personal & communication sector stmicroelectronics
vl6624/VS6624 package mechanical data 99/106 figure 39. package outline fpc module VS6624p0lp 4.5 1.20 7.65 @ datum a b 0.70 b (1) 1.2 4.00 0.10 (1) 1.15 0.15 1.00 12.92 4.60 0.30 2.83 0 . 0 5 1 . 0 0.25 ref 6.45 ref 0.30 7.10 22.50 4.00 1.2 0.07 0.10 8.00 - 0.05 +0.25 in mm do not scale a b c d e f a b c d e f sheet scale 2 1 3 4 5 6 78 1 3 2 7 6 8 title material finish and will not be copied or loaned without the 0.10 sig. date drawn written permission of stmicroelectronics. surface finish 1.6 microns tolerances, unless otherwise stated all dimensions in mm part no. interpret drawing per bs308, 3rd angle projection linear 0 place decimals 0 0.10 1 place decimals 0.0 0.07 2 place decimals 0.00 0.05 angular 0.25 degrees diameter +0.10/-0.00 position this drawing is the property of stmicroelectronics all dimensions home, personal & communications sector notes: 1) to optical axis of camera. a ref 0.15 1.57 6.16 0.30 3.96 0.15 1 of 2 624 camera outline generic flex version 7899934 revisions zone rev. description date 1 1st release for comment 02/09/05 2 tolerances and flex position and length changed from 21.95 15/09/2005 3 polarisation tab added 19/09/2005 4 sht 1, module height revised sht 2, top of scene rotated 90 degrees 22/09/2005 5 tab rotated 90 deg. 7.63 was 7.65, dim 1.13 added 26/09/2005 a 1st release into adcs dim 8.00 was +/-0.05, dim 4.60 was +/- 0.05 27/09/2005 stmicroelectronics copyright stmicroelectronics company confidential company confidential com unauthorized reproduction and communication strictly prohibited document 7899934 revision a controlled document (check latest revision) date 15-mar-2006 page: 1/2
package mechanical data vl6624/VS6624 100/106 figure 40. package outline fpc module VS6624p0lp om a 6 8 4.40 at datum a 2 of 2 624 camera outline generic flex version gnd 1. hsync 2. vsync 3. scl 4. clk 5. sda 6. vdd 7. avdd 8. pclk 9. ce 10. do 5 11. do 4 12. gnd 13. do 3 14. do 2 15. do 1 16. do 0 17. do 6 18. do 7 19. fso 20. 7899934 top of scene a b c d e f a b c d e f sheet scale 2 1 3 4 5 6 78 1 3 2 7 6 8 title material finish tolerances, unless otherwise stated linear 0 place decimals 0 1.0 1 place decimals 0.0 0.10 2 place decimals 0.00 0.07 angular 0.25 degrees diameter +0.10/-0.00 position 0.10 surface finish 1.6 microns interpret drawing per bs308, 3rd angle projection all dimensions in mm this drawing is the property of stmicroelectronics and will not be copied or loaned without the written permission of stmicroelectronics. drawn sig. date part no. all dimensions in mm do not scale home, personal & communication sector molex type 55560-0201, board - board conn http://www.molex.com/pdm_docs/sd/555600207_sd.pdf 1 10 11 20 pin out information stmicroelectronics copyright stmicroelectronics company confidential company confidential com unauthorized reproduction and communication strictly prohibited document 7899934 revision a controlled document (check latest revision) date 15-mar-2006 page: 2/2
vl6624/VS6624 package mechanical data 101/106 15.2 lga in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. table 52. lga package mechanical data data book (mm) symbol min. typ. max. a 1.80 1.90 2.00 a4 0.35 0.4 0.45 a5 0.7 0.8 0.9 b1 2.0 b2 3.5 b3 0.55 b 0.25 0.30 0.35 d 9.90 10.00 10.10 d1 9.60 9.70 9.80 d2 5 d4 5.4 e0.8 e 9.90 10.00 10.10 e1 9.60 9.70 9.80 e2 5 e4 4.5 g 1.0 1.1 1.2 g1 1 g2 0.3 0.4 0.5 g3 0.8 0.9 1.0 g4 0.8 h 0.8 0.9 1.0 h1 0.8 h2 0.3 0.4 0.5 i 3.95 4.05 4.15 j4.1 k0.3
package mechanical data vl6624/VS6624 102/106 phi 456 z1.65 l 0.7 0.8 0.9 bbb 0.01 ccc 0.1 ddd 0.08 eee 0.08 nd 9 ne 9 n36 table 52. lga package mechanical data (continued) data book (mm) symbol min. typ. max.
vl6624/VS6624 package mechanical data 103/106 figure 41. vl6524qomh outline drawing
ordering information vl6624/VS6624 104/106 16 ordering information table 53. vl6524 pin assignment pin signal pin signal pin signal pin signal 1 avdd 10 gnd 19 dio7 28 gnd 2 gnd 11 nc 20 dio6 29 pclk 3 sda 12 nc 21 dio5 30 vdd 4 scl 13 nc 22 dio4 31 nc 5ce14nc23vdd32nc 6 vdd 15 avdd 24 dio3 33 nc 7 clk 16 hsync 25 dio2 34 nc 8 gnd 17 vsync 26 dio1 35 nc 9fso18gnd27dio036gnd table 54. order codes part number package VS6624p0lp smop2 vga 8x8, flex VS6624q0kp smop2 vga 8x8, socket vl6624qomh lga 10x10x1.90 mm
vl6624/VS6624 revision history 105/106 17 revision history table 55. document revision history date revision changes 1-feb-2006 1 initial release. 14-apr-2006 2 updated table 51: parallel data interface timings . updated module outline drawing s figure 39 and figure 40 15-jun-2006 3 updated v il values in figure 45: dc electrical characteristics . updated figure 33: voltage level specification . added average sensitivity and spectral response sections in section 12: optical specifications . updated the applications and the document title on cover page. moved order codes to chapter 16: ordering information . 06-nov-2006 4 added vl6624 reference and lga outline drawings and dimensions. 06-dec-2006 5 corrected the part number for lga plug-in in ta bl e 5 4 . 08-jan-2007 6 corrected the optical format in table 41: optical specifications 02-jul-2007 7 updated the list of applications on the cover page. updated the table 16: ordering information . added chapter 14: user precaution .
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